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airliedairlied
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Merge tag 'amd-drm-fixes-6.7-2023-12-20' of https://gitlab.freedesktop.org/agd5f/linux into drm-fixes
amd-drm-fixes-6.7-2023-12-20: amdgpu: - DCN 3.5 fixes - DCN 3.2 SubVP fix - GPUVM fix amdkfd: - SVM fix for APUs Signed-off-by: Dave Airlie <airlied@redhat.com> From: Alex Deucher <alexander.deucher@amd.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231220164845.4975-1-alexander.deucher@amd.com
2 parents ceb6a6f + 4a0057a commit b7ef7ca

7 files changed

Lines changed: 55 additions & 27 deletions

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‎drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -285,6 +285,7 @@ static void amdgpu_vm_bo_reset_state_machine(struct amdgpu_vm *vm)
285285
list_for_each_entry_safe(vm_bo, tmp, &vm->idle, vm_status) {
286286
struct amdgpu_bo *bo = vm_bo->bo;
287287

288+
vm_bo->moved = true;
288289
if (!bo || bo->tbo.type != ttm_bo_type_kernel)
289290
list_move(&vm_bo->vm_status, &vm_bo->vm->moved);
290291
else if (bo->parent)

‎drivers/gpu/drm/amd/amdkfd/kfd_svm.c‎

Lines changed: 12 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1653,18 +1653,24 @@ static int svm_range_validate_and_map(struct mm_struct *mm,
16531653
if (test_bit(gpuidx, prange->bitmap_access))
16541654
bitmap_set(ctx->bitmap, gpuidx, 1);
16551655
}
1656+
1657+
/*
1658+
* If prange is already mapped or with always mapped flag,
1659+
* update mapping on GPUs with ACCESS attribute
1660+
*/
1661+
if (bitmap_empty(ctx->bitmap, MAX_GPU_INSTANCE)) {
1662+
if (prange->mapped_to_gpu ||
1663+
prange->flags & KFD_IOCTL_SVM_FLAG_GPU_ALWAYS_MAPPED)
1664+
bitmap_copy(ctx->bitmap, prange->bitmap_access, MAX_GPU_INSTANCE);
1665+
}
16561666
} else {
16571667
bitmap_or(ctx->bitmap, prange->bitmap_access,
16581668
prange->bitmap_aip, MAX_GPU_INSTANCE);
16591669
}
16601670

16611671
if (bitmap_empty(ctx->bitmap, MAX_GPU_INSTANCE)) {
1662-
bitmap_copy(ctx->bitmap, prange->bitmap_access, MAX_GPU_INSTANCE);
1663-
if (!prange->mapped_to_gpu ||
1664-
bitmap_empty(ctx->bitmap, MAX_GPU_INSTANCE)) {
1665-
r = 0;
1666-
goto free_ctx;
1667-
}
1672+
r = 0;
1673+
goto free_ctx;
16681674
}
16691675

16701676
if (prange->actual_loc && !prange->ttm_res) {

‎drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c‎

Lines changed: 15 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -1014,13 +1014,20 @@ static enum bp_result get_ss_info_v4_5(
10141014
DC_LOG_BIOS("AS_SIGNAL_TYPE_HDMI ss_percentage: %d\n", ss_info->spread_spectrum_percentage);
10151015
break;
10161016
case AS_SIGNAL_TYPE_DISPLAY_PORT:
1017-
ss_info->spread_spectrum_percentage =
1017+
if (bp->base.integrated_info) {
1018+
DC_LOG_BIOS("gpuclk_ss_percentage (unit of 0.001 percent): %d\n", bp->base.integrated_info->gpuclk_ss_percentage);
1019+
ss_info->spread_spectrum_percentage =
1020+
bp->base.integrated_info->gpuclk_ss_percentage;
1021+
ss_info->type.CENTER_MODE =
1022+
bp->base.integrated_info->gpuclk_ss_type;
1023+
} else {
1024+
ss_info->spread_spectrum_percentage =
10181025
disp_cntl_tbl->dp_ss_percentage;
1019-
ss_info->spread_spectrum_range =
1026+
ss_info->spread_spectrum_range =
10201027
disp_cntl_tbl->dp_ss_rate_10hz * 10;
1021-
if (disp_cntl_tbl->dp_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE)
1022-
ss_info->type.CENTER_MODE = true;
1023-
1028+
if (disp_cntl_tbl->dp_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE)
1029+
ss_info->type.CENTER_MODE = true;
1030+
}
10241031
DC_LOG_BIOS("AS_SIGNAL_TYPE_DISPLAY_PORT ss_percentage: %d\n", ss_info->spread_spectrum_percentage);
10251032
break;
10261033
case AS_SIGNAL_TYPE_GPU_PLL:
@@ -2386,13 +2393,7 @@ static enum bp_result get_vram_info_v30(
23862393
return BP_RESULT_BADBIOSTABLE;
23872394

23882395
info->num_chans = info_v30->channel_num;
2389-
/* As suggested by VBIOS we should always use
2390-
* dram_channel_width_bytes = 2 when using VRAM
2391-
* table version 3.0. This is because the channel_width
2392-
* param in the VRAM info table is changed in 7000 series and
2393-
* no longer represents the memory channel width.
2394-
*/
2395-
info->dram_channel_width_bytes = 2;
2396+
info->dram_channel_width_bytes = (1 << info_v30->channel_width) / 8;
23962397

23972398
return result;
23982399
}
@@ -2820,6 +2821,8 @@ static enum bp_result get_integrated_info_v2_2(
28202821
info->ma_channel_number = info_v2_2->umachannelnumber;
28212822
info->dp_ss_control =
28222823
le16_to_cpu(info_v2_2->reserved1);
2824+
info->gpuclk_ss_percentage = info_v2_2->gpuclk_ss_percentage;
2825+
info->gpuclk_ss_type = info_v2_2->gpuclk_ss_type;
28232826

28242827
for (i = 0; i < NUMBER_OF_UCHAR_FOR_GUID; ++i) {
28252828
info->ext_disp_conn_info.gu_id[i] =

‎drivers/gpu/drm/amd/display/dc/core/dc.c‎

Lines changed: 18 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -5095,18 +5095,28 @@ void dc_mclk_switch_using_fw_based_vblank_stretch_shut_down(struct dc *dc)
50955095
*/
50965096
bool dc_is_dmub_outbox_supported(struct dc *dc)
50975097
{
5098-
/* DCN31 B0 USB4 DPIA needs dmub notifications for interrupts */
5099-
if (dc->ctx->asic_id.chip_family == FAMILY_YELLOW_CARP &&
5100-
dc->ctx->asic_id.hw_internal_rev == YELLOW_CARP_B0 &&
5101-
!dc->debug.dpia_debug.bits.disable_dpia)
5102-
return true;
5098+
switch (dc->ctx->asic_id.chip_family) {
51035099

5104-
if (dc->ctx->asic_id.chip_family == AMDGPU_FAMILY_GC_11_0_1 &&
5105-
!dc->debug.dpia_debug.bits.disable_dpia)
5106-
return true;
5100+
case FAMILY_YELLOW_CARP:
5101+
/* DCN31 B0 USB4 DPIA needs dmub notifications for interrupts */
5102+
if (dc->ctx->asic_id.hw_internal_rev == YELLOW_CARP_B0 &&
5103+
!dc->debug.dpia_debug.bits.disable_dpia)
5104+
return true;
5105+
break;
5106+
5107+
case AMDGPU_FAMILY_GC_11_0_1:
5108+
case AMDGPU_FAMILY_GC_11_5_0:
5109+
if (!dc->debug.dpia_debug.bits.disable_dpia)
5110+
return true;
5111+
break;
5112+
5113+
default:
5114+
break;
5115+
}
51075116

51085117
/* dmub aux needs dmub notifications to be enabled */
51095118
return dc->debug.enable_dmub_aux_for_legacy_ddc;
5119+
51105120
}
51115121

51125122
/**

‎drivers/gpu/drm/amd/display/dc/dml2/display_mode_core.c‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -5420,7 +5420,7 @@ static void CalculateOutputLink(
54205420
*OutBpp = TruncToValidBPP((1 - Downspreading / 100) * 13500, OutputLinkDPLanes, HTotal, HActive, PixelClockBackEnd, ForcedOutputLinkBPP, LinkDSCEnable, Output,
54215421
OutputFormat, DSCInputBitPerComponent, NumberOfDSCSlices, (dml_uint_t)AudioSampleRate, AudioSampleLayout, ODMModeNoDSC, ODMModeDSC, RequiredSlots);
54225422

5423-
if (OutBpp == 0 && PHYCLKD32PerState < 20000 / 32 && DSCEnable == dml_dsc_enable_if_necessary && ForcedOutputLinkBPP == 0) {
5423+
if (*OutBpp == 0 && PHYCLKD32PerState < 20000 / 32 && DSCEnable == dml_dsc_enable_if_necessary && ForcedOutputLinkBPP == 0) {
54245424
*RequiresDSC = true;
54255425
LinkDSCEnable = true;
54265426
*OutBpp = TruncToValidBPP((1 - Downspreading / 100) * 13500, OutputLinkDPLanes, HTotal, HActive, PixelClockBackEnd, ForcedOutputLinkBPP, LinkDSCEnable, Output,

‎drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c‎

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -960,6 +960,12 @@ void dcn32_init_hw(struct dc *dc)
960960
dc->caps.dmub_caps.subvp_psr = dc->ctx->dmub_srv->dmub->feature_caps.subvp_psr_support;
961961
dc->caps.dmub_caps.gecc_enable = dc->ctx->dmub_srv->dmub->feature_caps.gecc_enable;
962962
dc->caps.dmub_caps.mclk_sw = dc->ctx->dmub_srv->dmub->feature_caps.fw_assisted_mclk_switch;
963+
964+
if (dc->ctx->dmub_srv->dmub->fw_version <
965+
DMUB_FW_VERSION(7, 0, 35)) {
966+
dc->debug.force_disable_subvp = true;
967+
dc->debug.disable_fpo_optimizations = true;
968+
}
963969
}
964970
}
965971

‎drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -417,6 +417,8 @@ struct integrated_info {
417417
/* V2.1 */
418418
struct edp_info edp1_info;
419419
struct edp_info edp2_info;
420+
uint32_t gpuclk_ss_percentage;
421+
uint32_t gpuclk_ss_type;
420422
};
421423

422424
/*

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