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AngeloGioacchino Del Regnombgg
AngeloGioacchino Del Regno
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mbgg
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soc: mediatek: pwrap: Add support for MT6795 Helio X10
Add the necessary bits to support the MT6795 Helio X10 smartphone SoC: this is always paired with a MT6331 PMIC, with MT6332 companion. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com> Link: https://lore.kernel.org/r/20230412131216.198313-7-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
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‎drivers/soc/mediatek/mtk-pmic-wrap.c‎

Lines changed: 135 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -639,6 +639,91 @@ static int mt6779_regs[] = {
639639
[PWRAP_WACS2_VLDCLR] = 0xC28,
640640
};
641641

642+
static int mt6795_regs[] = {
643+
[PWRAP_MUX_SEL] = 0x0,
644+
[PWRAP_WRAP_EN] = 0x4,
645+
[PWRAP_DIO_EN] = 0x8,
646+
[PWRAP_SIDLY] = 0xc,
647+
[PWRAP_RDDMY] = 0x10,
648+
[PWRAP_SI_CK_CON] = 0x14,
649+
[PWRAP_CSHEXT_WRITE] = 0x18,
650+
[PWRAP_CSHEXT_READ] = 0x1c,
651+
[PWRAP_CSLEXT_START] = 0x20,
652+
[PWRAP_CSLEXT_END] = 0x24,
653+
[PWRAP_STAUPD_PRD] = 0x28,
654+
[PWRAP_STAUPD_GRPEN] = 0x2c,
655+
[PWRAP_EINT_STA0_ADR] = 0x30,
656+
[PWRAP_EINT_STA1_ADR] = 0x34,
657+
[PWRAP_STAUPD_MAN_TRIG] = 0x40,
658+
[PWRAP_STAUPD_STA] = 0x44,
659+
[PWRAP_WRAP_STA] = 0x48,
660+
[PWRAP_HARB_INIT] = 0x4c,
661+
[PWRAP_HARB_HPRIO] = 0x50,
662+
[PWRAP_HIPRIO_ARB_EN] = 0x54,
663+
[PWRAP_HARB_STA0] = 0x58,
664+
[PWRAP_HARB_STA1] = 0x5c,
665+
[PWRAP_MAN_EN] = 0x60,
666+
[PWRAP_MAN_CMD] = 0x64,
667+
[PWRAP_MAN_RDATA] = 0x68,
668+
[PWRAP_MAN_VLDCLR] = 0x6c,
669+
[PWRAP_WACS0_EN] = 0x70,
670+
[PWRAP_INIT_DONE0] = 0x74,
671+
[PWRAP_WACS0_CMD] = 0x78,
672+
[PWRAP_WACS0_RDATA] = 0x7c,
673+
[PWRAP_WACS0_VLDCLR] = 0x80,
674+
[PWRAP_WACS1_EN] = 0x84,
675+
[PWRAP_INIT_DONE1] = 0x88,
676+
[PWRAP_WACS1_CMD] = 0x8c,
677+
[PWRAP_WACS1_RDATA] = 0x90,
678+
[PWRAP_WACS1_VLDCLR] = 0x94,
679+
[PWRAP_WACS2_EN] = 0x98,
680+
[PWRAP_INIT_DONE2] = 0x9c,
681+
[PWRAP_WACS2_CMD] = 0xa0,
682+
[PWRAP_WACS2_RDATA] = 0xa4,
683+
[PWRAP_WACS2_VLDCLR] = 0xa8,
684+
[PWRAP_INT_EN] = 0xac,
685+
[PWRAP_INT_FLG_RAW] = 0xb0,
686+
[PWRAP_INT_FLG] = 0xb4,
687+
[PWRAP_INT_CLR] = 0xb8,
688+
[PWRAP_SIG_ADR] = 0xbc,
689+
[PWRAP_SIG_MODE] = 0xc0,
690+
[PWRAP_SIG_VALUE] = 0xc4,
691+
[PWRAP_SIG_ERRVAL] = 0xc8,
692+
[PWRAP_CRC_EN] = 0xcc,
693+
[PWRAP_TIMER_EN] = 0xd0,
694+
[PWRAP_TIMER_STA] = 0xd4,
695+
[PWRAP_WDT_UNIT] = 0xd8,
696+
[PWRAP_WDT_SRC_EN] = 0xdc,
697+
[PWRAP_WDT_FLG] = 0xe0,
698+
[PWRAP_DEBUG_INT_SEL] = 0xe4,
699+
[PWRAP_DVFS_ADR0] = 0xe8,
700+
[PWRAP_DVFS_WDATA0] = 0xec,
701+
[PWRAP_DVFS_ADR1] = 0xf0,
702+
[PWRAP_DVFS_WDATA1] = 0xf4,
703+
[PWRAP_DVFS_ADR2] = 0xf8,
704+
[PWRAP_DVFS_WDATA2] = 0xfc,
705+
[PWRAP_DVFS_ADR3] = 0x100,
706+
[PWRAP_DVFS_WDATA3] = 0x104,
707+
[PWRAP_DVFS_ADR4] = 0x108,
708+
[PWRAP_DVFS_WDATA4] = 0x10c,
709+
[PWRAP_DVFS_ADR5] = 0x110,
710+
[PWRAP_DVFS_WDATA5] = 0x114,
711+
[PWRAP_DVFS_ADR6] = 0x118,
712+
[PWRAP_DVFS_WDATA6] = 0x11c,
713+
[PWRAP_DVFS_ADR7] = 0x120,
714+
[PWRAP_DVFS_WDATA7] = 0x124,
715+
[PWRAP_SPMINF_STA] = 0x128,
716+
[PWRAP_CIPHER_KEY_SEL] = 0x12c,
717+
[PWRAP_CIPHER_IV_SEL] = 0x130,
718+
[PWRAP_CIPHER_EN] = 0x134,
719+
[PWRAP_CIPHER_RDY] = 0x138,
720+
[PWRAP_CIPHER_MODE] = 0x13c,
721+
[PWRAP_CIPHER_SWRST] = 0x140,
722+
[PWRAP_DCM_EN] = 0x144,
723+
[PWRAP_DCM_DBC_PRD] = 0x148,
724+
[PWRAP_EXT_CK] = 0x14c,
725+
};
726+
642727
static int mt6797_regs[] = {
643728
[PWRAP_MUX_SEL] = 0x0,
644729
[PWRAP_WRAP_EN] = 0x4,
@@ -1230,6 +1315,7 @@ enum pwrap_type {
12301315
PWRAP_MT2701,
12311316
PWRAP_MT6765,
12321317
PWRAP_MT6779,
1318+
PWRAP_MT6795,
12331319
PWRAP_MT6797,
12341320
PWRAP_MT6873,
12351321
PWRAP_MT7622,
@@ -1650,6 +1736,20 @@ static void pwrap_init_chip_select_ext(struct pmic_wrapper *wrp, u8 hext_write,
16501736
static int pwrap_common_init_reg_clock(struct pmic_wrapper *wrp)
16511737
{
16521738
switch (wrp->master->type) {
1739+
case PWRAP_MT6795:
1740+
if (wrp->slave->type == PMIC_MT6331) {
1741+
const u32 *dew_regs = wrp->slave->dew_regs;
1742+
1743+
pwrap_write(wrp, dew_regs[PWRAP_DEW_RDDMY_NO], 0x8);
1744+
1745+
if (wrp->slave->comp_type == PMIC_MT6332) {
1746+
dew_regs = wrp->slave->comp_dew_regs;
1747+
pwrap_write(wrp, dew_regs[PWRAP_DEW_RDDMY_NO], 0x8);
1748+
}
1749+
}
1750+
pwrap_writel(wrp, 0x88, PWRAP_RDDMY);
1751+
pwrap_init_chip_select_ext(wrp, 15, 15, 15, 15);
1752+
break;
16531753
case PWRAP_MT8173:
16541754
pwrap_init_chip_select_ext(wrp, 0, 4, 2, 2);
16551755
break;
@@ -1744,6 +1844,7 @@ static int pwrap_init_cipher(struct pmic_wrapper *wrp)
17441844
case PWRAP_MT2701:
17451845
case PWRAP_MT6765:
17461846
case PWRAP_MT6779:
1847+
case PWRAP_MT6795:
17471848
case PWRAP_MT6797:
17481849
case PWRAP_MT8173:
17491850
case PWRAP_MT8186:
@@ -1914,6 +2015,19 @@ static int pwrap_mt2701_init_soc_specific(struct pmic_wrapper *wrp)
19142015
return 0;
19152016
}
19162017

2018+
static int pwrap_mt6795_init_soc_specific(struct pmic_wrapper *wrp)
2019+
{
2020+
pwrap_writel(wrp, 0xf, PWRAP_STAUPD_GRPEN);
2021+
2022+
if (wrp->slave->type == PMIC_MT6331)
2023+
pwrap_writel(wrp, 0x1b4, PWRAP_EINT_STA0_ADR);
2024+
2025+
if (wrp->slave->comp_type == PMIC_MT6332)
2026+
pwrap_writel(wrp, 0x8112, PWRAP_EINT_STA1_ADR);
2027+
2028+
return 0;
2029+
}
2030+
19172031
static int pwrap_mt7622_init_soc_specific(struct pmic_wrapper *wrp)
19182032
{
19192033
pwrap_writel(wrp, 0, PWRAP_STAUPD_PRD);
@@ -1949,10 +2063,16 @@ static int pwrap_init(struct pmic_wrapper *wrp)
19492063
if (wrp->rstc_bridge)
19502064
reset_control_reset(wrp->rstc_bridge);
19512065

1952-
if (wrp->master->type == PWRAP_MT8173) {
2066+
switch (wrp->master->type) {
2067+
case PWRAP_MT6795:
2068+
fallthrough;
2069+
case PWRAP_MT8173:
19532070
/* Enable DCM */
19542071
pwrap_writel(wrp, 3, PWRAP_DCM_EN);
19552072
pwrap_writel(wrp, 0, PWRAP_DCM_DBC_PRD);
2073+
break;
2074+
default:
2075+
break;
19562076
}
19572077

19582078
if (HAS_CAP(wrp->slave->caps, PWRAP_SLV_CAP_SPI)) {
@@ -2185,6 +2305,19 @@ static const struct pmic_wrapper_type pwrap_mt6779 = {
21852305
.init_soc_specific = NULL,
21862306
};
21872307

2308+
static const struct pmic_wrapper_type pwrap_mt6795 = {
2309+
.regs = mt6795_regs,
2310+
.type = PWRAP_MT6795,
2311+
.arb_en_all = 0x3f,
2312+
.int_en_all = ~(u32)(BIT(31) | BIT(2) | BIT(1)),
2313+
.int1_en_all = 0,
2314+
.spi_w = PWRAP_MAN_CMD_SPI_WRITE,
2315+
.wdt_src = PWRAP_WDT_SRC_MASK_NO_STAUPD,
2316+
.caps = PWRAP_CAP_RESET | PWRAP_CAP_DCM,
2317+
.init_reg_clock = pwrap_common_init_reg_clock,
2318+
.init_soc_specific = pwrap_mt6795_init_soc_specific,
2319+
};
2320+
21882321
static const struct pmic_wrapper_type pwrap_mt6797 = {
21892322
.regs = mt6797_regs,
21902323
.type = PWRAP_MT6797,
@@ -2318,6 +2451,7 @@ static const struct of_device_id of_pwrap_match_tbl[] = {
23182451
{ .compatible = "mediatek,mt2701-pwrap", .data = &pwrap_mt2701 },
23192452
{ .compatible = "mediatek,mt6765-pwrap", .data = &pwrap_mt6765 },
23202453
{ .compatible = "mediatek,mt6779-pwrap", .data = &pwrap_mt6779 },
2454+
{ .compatible = "mediatek,mt6795-pwrap", .data = &pwrap_mt6795 },
23212455
{ .compatible = "mediatek,mt6797-pwrap", .data = &pwrap_mt6797 },
23222456
{ .compatible = "mediatek,mt6873-pwrap", .data = &pwrap_mt6873 },
23232457
{ .compatible = "mediatek,mt7622-pwrap", .data = &pwrap_mt7622 },

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