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jason-jh.lin
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soc: mediatek: add mtk-mmsys support for mt8195 vdosys0
1. Add mt8195 mmsys compatible for 2 vdosys. 2. Add io_start into each driver data of mt8195 vdosys. 3. Add get match data function to identify mmsys by io_start. 4. Add mt8195 routing table settings of vdosys0. Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: CK Hu <ck.hu@mediatek.com> Link: https://lore.kernel.org/r/20220419094143.9561-2-jason-jh.lin@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
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‎drivers/soc/mediatek/mt8195-mmsys.h‎

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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef __SOC_MEDIATEK_MT8195_MMSYS_H
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#define __SOC_MEDIATEK_MT8195_MMSYS_H
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#define MT8195_VDO0_OVL_MOUT_EN 0xf14
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#define MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0 BIT(0)
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#define MT8195_MOUT_DISP_OVL0_TO_DISP_WDMA0 BIT(1)
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#define MT8195_MOUT_DISP_OVL0_TO_DISP_OVL1 BIT(2)
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#define MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1 BIT(4)
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#define MT8195_MOUT_DISP_OVL1_TO_DISP_WDMA1 BIT(5)
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#define MT8195_MOUT_DISP_OVL1_TO_DISP_OVL0 BIT(6)
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#define MT8195_VDO0_SEL_IN 0xf34
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#define MT8195_SEL_IN_VPP_MERGE_FROM_MASK GENMASK(1, 0)
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#define MT8195_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT (0 << 0)
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#define MT8195_SEL_IN_VPP_MERGE_FROM_DISP_DITHER1 (1 << 0)
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#define MT8195_SEL_IN_VPP_MERGE_FROM_VDO1_VIRTUAL0 (2 << 0)
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#define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_MASK GENMASK(4, 4)
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#define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0 (0 << 4)
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#define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_VPP_MERGE (1 << 4)
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#define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_MASK GENMASK(5, 5)
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#define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_DISP_DITHER1 (0 << 5)
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#define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_VPP_MERGE (1 << 5)
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#define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK GENMASK(8, 8)
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#define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE (0 << 8)
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#define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT (1 << 8)
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#define MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK GENMASK(9, 9)
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#define MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT (0 << 9)
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#define MT8195_SEL_IN_DP_INTF0_FROM_MASK GENMASK(13, 12)
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#define MT8195_SEL_IN_DP_INTF0_FROM_DSC_WRAP1_OUT (0 << 0)
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#define MT8195_SEL_IN_DP_INTF0_FROM_VPP_MERGE (1 << 12)
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#define MT8195_SEL_IN_DP_INTF0_FROM_VDO1_VIRTUAL0 (2 << 12)
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#define MT8195_SEL_IN_DSI0_FROM_MASK GENMASK(16, 16)
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#define MT8195_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT (0 << 16)
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#define MT8195_SEL_IN_DSI0_FROM_DISP_DITHER0 (1 << 16)
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#define MT8195_SEL_IN_DSI1_FROM_MASK GENMASK(17, 17)
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#define MT8195_SEL_IN_DSI1_FROM_DSC_WRAP1_OUT (0 << 17)
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#define MT8195_SEL_IN_DSI1_FROM_VPP_MERGE (1 << 17)
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#define MT8195_SEL_IN_DISP_WDMA1_FROM_MASK GENMASK(20, 20)
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#define MT8195_SEL_IN_DISP_WDMA1_FROM_DISP_OVL1 (0 << 20)
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#define MT8195_SEL_IN_DISP_WDMA1_FROM_VPP_MERGE (1 << 20)
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#define MT8195_SEL_IN_DSC_WRAP1_FROM_MASK GENMASK(21, 21)
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#define MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN (0 << 21)
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#define MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1 (1 << 21)
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#define MT8195_SEL_IN_DISP_WDMA0_FROM_MASK GENMASK(22, 22)
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#define MT8195_SEL_IN_DISP_WDMA0_FROM_DISP_OVL0 (0 << 22)
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#define MT8195_VDO0_SEL_OUT 0xf38
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#define MT8195_SOUT_DISP_DITHER0_TO_MASK BIT(0)
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#define MT8195_SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN (0 << 0)
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#define MT8195_SOUT_DISP_DITHER0_TO_DSI0 (1 << 0)
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#define MT8195_SOUT_DISP_DITHER1_TO_MASK GENMASK(2, 1)
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#define MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_IN (0 << 1)
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#define MT8195_SOUT_DISP_DITHER1_TO_VPP_MERGE (1 << 1)
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#define MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT (2 << 1)
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#define MT8195_SOUT_VDO1_VIRTUAL0_TO_MASK GENMASK(4, 4)
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#define MT8195_SOUT_VDO1_VIRTUAL0_TO_VPP_MERGE (0 << 4)
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#define MT8195_SOUT_VDO1_VIRTUAL0_TO_DP_INTF0 (1 << 4)
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#define MT8195_SOUT_VPP_MERGE_TO_MASK GENMASK(10, 8)
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#define MT8195_SOUT_VPP_MERGE_TO_DSI1 (0 << 8)
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#define MT8195_SOUT_VPP_MERGE_TO_DP_INTF0 (1 << 8)
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#define MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0 (2 << 8)
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#define MT8195_SOUT_VPP_MERGE_TO_DISP_WDMA1 (3 << 8)
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#define MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP0_IN (4 << 8)
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#define MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN_MASK GENMASK(11, 11)
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#define MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN (0 << 11)
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#define MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK GENMASK(13, 12)
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#define MT8195_SOUT_DSC_WRAP0_OUT_TO_DSI0 (0 << 12)
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#define MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0 (1 << 12)
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#define MT8195_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE (2 << 12)
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#define MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK GENMASK(17, 16)
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#define MT8195_SOUT_DSC_WRAP1_OUT_TO_DSI1 (0 << 16)
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#define MT8195_SOUT_DSC_WRAP1_OUT_TO_DP_INTF0 (1 << 16)
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#define MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0 (2 << 16)
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#define MT8195_SOUT_DSC_WRAP1_OUT_TO_VPP_MERGE (3 << 16)
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static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = {
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{
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DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
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MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0,
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MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0
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}, {
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DDP_COMPONENT_OVL0, DDP_COMPONENT_WDMA0,
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MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL0_TO_DISP_WDMA0,
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MT8195_MOUT_DISP_OVL0_TO_DISP_WDMA0
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}, {
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DDP_COMPONENT_OVL0, DDP_COMPONENT_OVL1,
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MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL0_TO_DISP_OVL1,
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MT8195_MOUT_DISP_OVL0_TO_DISP_OVL1
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}, {
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DDP_COMPONENT_OVL1, DDP_COMPONENT_RDMA1,
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MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1,
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MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1
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}, {
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DDP_COMPONENT_OVL1, DDP_COMPONENT_WDMA1,
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MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL1_TO_DISP_WDMA1,
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MT8195_MOUT_DISP_OVL1_TO_DISP_WDMA1
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}, {
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DDP_COMPONENT_OVL1, DDP_COMPONENT_OVL0,
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MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL1_TO_DISP_OVL0,
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MT8195_MOUT_DISP_OVL1_TO_DISP_OVL0
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}, {
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DDP_COMPONENT_DSC0, DDP_COMPONENT_MERGE0,
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MT8195_VDO0_SEL_IN, MT8195_SEL_IN_VPP_MERGE_FROM_MASK,
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MT8195_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT
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}, {
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DDP_COMPONENT_DITHER1, DDP_COMPONENT_MERGE0,
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MT8195_VDO0_SEL_IN, MT8195_SEL_IN_VPP_MERGE_FROM_MASK,
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MT8195_SEL_IN_VPP_MERGE_FROM_DISP_DITHER1
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}, {
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DDP_COMPONENT_MERGE5, DDP_COMPONENT_MERGE0,
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MT8195_VDO0_SEL_IN, MT8195_SEL_IN_VPP_MERGE_FROM_MASK,
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MT8195_SEL_IN_VPP_MERGE_FROM_VDO1_VIRTUAL0
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}, {
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DDP_COMPONENT_DITHER, DDP_COMPONENT_DSC0,
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MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP0_IN_FROM_MASK,
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MT8195_SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0
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}, {
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DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC0,
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MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP0_IN_FROM_MASK,
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MT8195_SEL_IN_DSC_WRAP0_IN_FROM_VPP_MERGE
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}, {
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DDP_COMPONENT_DITHER1, DDP_COMPONENT_DSC1,
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MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_IN_FROM_MASK,
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MT8195_SEL_IN_DSC_WRAP1_IN_FROM_DISP_DITHER1
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}, {
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DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC1,
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MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_IN_FROM_MASK,
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MT8195_SEL_IN_DSC_WRAP1_IN_FROM_VPP_MERGE
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}, {
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DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF1,
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MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
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MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE
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}, {
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DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI0,
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MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
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MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE
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}, {
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DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI1,
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MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
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MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE
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}, {
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DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF1,
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MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
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MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT
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}, {
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DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI0,
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MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
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MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT
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}, {
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DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI1,
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MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
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MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT
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}, {
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DDP_COMPONENT_DSC0, DDP_COMPONENT_DP_INTF1,
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MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK,
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MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT
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}, {
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DDP_COMPONENT_DSC0, DDP_COMPONENT_DPI0,
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MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK,
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MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT
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}, {
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DDP_COMPONENT_DSC0, DDP_COMPONENT_DPI1,
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MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK,
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MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT
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}, {
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DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF0,
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MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DP_INTF0_FROM_MASK,
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MT8195_SEL_IN_DP_INTF0_FROM_DSC_WRAP1_OUT
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}, {
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DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF0,
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MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DP_INTF0_FROM_MASK,
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MT8195_SEL_IN_DP_INTF0_FROM_VPP_MERGE
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}, {
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DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF0,
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MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DP_INTF0_FROM_MASK,
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MT8195_SEL_IN_DP_INTF0_FROM_VDO1_VIRTUAL0
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}, {
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DDP_COMPONENT_DSC0, DDP_COMPONENT_DSI0,
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MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI0_FROM_MASK,
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MT8195_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT
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}, {
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DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
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MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI0_FROM_MASK,
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MT8195_SEL_IN_DSI0_FROM_DISP_DITHER0
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}, {
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DDP_COMPONENT_DSC1, DDP_COMPONENT_DSI1,
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MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI1_FROM_MASK,
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MT8195_SEL_IN_DSI1_FROM_DSC_WRAP1_OUT
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}, {
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DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSI1,
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MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI1_FROM_MASK,
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MT8195_SEL_IN_DSI1_FROM_VPP_MERGE
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}, {
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DDP_COMPONENT_OVL1, DDP_COMPONENT_WDMA1,
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MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DISP_WDMA1_FROM_MASK,
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MT8195_SEL_IN_DISP_WDMA1_FROM_DISP_OVL1
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}, {
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DDP_COMPONENT_MERGE0, DDP_COMPONENT_WDMA1,
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MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DISP_WDMA1_FROM_MASK,
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MT8195_SEL_IN_DISP_WDMA1_FROM_VPP_MERGE
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}, {
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DDP_COMPONENT_DSC1, DDP_COMPONENT_DSI1,
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MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
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MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
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}, {
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DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF0,
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MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
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MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
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}, {
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DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF1,
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MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
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MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
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}, {
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DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI0,
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MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
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MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
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}, {
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DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI1,
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MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
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MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
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}, {
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DDP_COMPONENT_DSC1, DDP_COMPONENT_MERGE0,
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MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
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MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
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}, {
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DDP_COMPONENT_DITHER1, DDP_COMPONENT_DSI1,
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MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
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MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1
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}, {
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DDP_COMPONENT_DITHER1, DDP_COMPONENT_DP_INTF0,
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MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
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MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1
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}, {
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DDP_COMPONENT_DITHER1, DDP_COMPONENT_DPI0,
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MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
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MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1
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}, {
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DDP_COMPONENT_DITHER1, DDP_COMPONENT_DPI1,
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MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
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MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1
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}, {
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DDP_COMPONENT_OVL0, DDP_COMPONENT_WDMA0,
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MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DISP_WDMA0_FROM_MASK,
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MT8195_SEL_IN_DISP_WDMA0_FROM_DISP_OVL0
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}, {
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DDP_COMPONENT_DITHER, DDP_COMPONENT_DSC0,
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MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER0_TO_MASK,
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MT8195_SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN
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}, {
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DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
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MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER0_TO_MASK,
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MT8195_SOUT_DISP_DITHER0_TO_DSI0
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}, {
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DDP_COMPONENT_DITHER1, DDP_COMPONENT_DSC1,
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MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
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MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_IN
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}, {
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DDP_COMPONENT_DITHER1, DDP_COMPONENT_MERGE0,
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MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
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MT8195_SOUT_DISP_DITHER1_TO_VPP_MERGE
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}, {
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DDP_COMPONENT_DITHER1, DDP_COMPONENT_DSI1,
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MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
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MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT
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}, {
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DDP_COMPONENT_DITHER1, DDP_COMPONENT_DP_INTF0,
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MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
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MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT
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}, {
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DDP_COMPONENT_DITHER1, DDP_COMPONENT_DP_INTF1,
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MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
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MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT
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}, {
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DDP_COMPONENT_DITHER1, DDP_COMPONENT_DPI0,
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MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
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MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT
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}, {
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DDP_COMPONENT_DITHER1, DDP_COMPONENT_DPI1,
281+
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
282+
MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT
283+
}, {
284+
DDP_COMPONENT_MERGE5, DDP_COMPONENT_MERGE0,
285+
MT8195_VDO0_SEL_OUT, MT8195_SOUT_VDO1_VIRTUAL0_TO_MASK,
286+
MT8195_SOUT_VDO1_VIRTUAL0_TO_VPP_MERGE
287+
}, {
288+
DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF0,
289+
MT8195_VDO0_SEL_OUT, MT8195_SOUT_VDO1_VIRTUAL0_TO_MASK,
290+
MT8195_SOUT_VDO1_VIRTUAL0_TO_DP_INTF0
291+
}, {
292+
DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSI1,
293+
MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
294+
MT8195_SOUT_VPP_MERGE_TO_DSI1
295+
}, {
296+
DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF0,
297+
MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
298+
MT8195_SOUT_VPP_MERGE_TO_DP_INTF0
299+
}, {
300+
DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF1,
301+
MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
302+
MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0
303+
}, {
304+
DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI0,
305+
MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
306+
MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0
307+
}, {
308+
DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI1,
309+
MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
310+
MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0
311+
}, {
312+
DDP_COMPONENT_MERGE0, DDP_COMPONENT_WDMA1,
313+
MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
314+
MT8195_SOUT_VPP_MERGE_TO_DISP_WDMA1
315+
}, {
316+
DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC0,
317+
MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
318+
MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP0_IN
319+
}, {
320+
DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC1,
321+
MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN_MASK,
322+
MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN
323+
}, {
324+
DDP_COMPONENT_DSC0, DDP_COMPONENT_DSI0,
325+
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
326+
MT8195_SOUT_DSC_WRAP0_OUT_TO_DSI0
327+
}, {
328+
DDP_COMPONENT_DSC0, DDP_COMPONENT_DP_INTF1,
329+
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
330+
MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0
331+
}, {
332+
DDP_COMPONENT_DSC0, DDP_COMPONENT_DPI0,
333+
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
334+
MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0
335+
}, {
336+
DDP_COMPONENT_DSC0, DDP_COMPONENT_DPI1,
337+
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
338+
MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0
339+
}, {
340+
DDP_COMPONENT_DSC0, DDP_COMPONENT_MERGE0,
341+
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
342+
MT8195_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE
343+
}, {
344+
DDP_COMPONENT_DSC1, DDP_COMPONENT_DSI1,
345+
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
346+
MT8195_SOUT_DSC_WRAP1_OUT_TO_DSI1
347+
}, {
348+
DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF0,
349+
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
350+
MT8195_SOUT_DSC_WRAP1_OUT_TO_DP_INTF0
351+
}, {
352+
DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF1,
353+
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
354+
MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0
355+
}, {
356+
DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI0,
357+
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
358+
MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0
359+
}, {
360+
DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI1,
361+
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
362+
MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0
363+
}, {
364+
DDP_COMPONENT_DSC1, DDP_COMPONENT_MERGE0,
365+
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
366+
MT8195_SOUT_DSC_WRAP1_OUT_TO_VPP_MERGE
367+
}
368+
};
369+
370+
#endif /* __SOC_MEDIATEK_MT8195_MMSYS_H */

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