Skip to content

Commit b91217d

Browse files
bebarinobebarino
committed
Merge branches 'clk-microchip', 'clk-lookup' and 'clk-st' into clk-next
 - Speed up clk_core_lookup() by using a hashtable * clk-microchip: ARM: at91: remove default values for PMC_PLL_ACR clk: at91: add ACR in all PLL settings clk: at91: sam9x7: Add peripheral clock id for pmecc clk: at91: clk-master: Add check for divide by 3 clk: at91: clk-sam9x60-pll: force write to PLL_UPDT register ARM: at91: pm: save and restore ACR during PLL disable/enable * clk-lookup: clk: Use hashtable for global clk lookups clk: Sort include statements * clk-st: dt-bindings: stm32: cosmetic fixes for STM32MP25 clock and reset bindings clk: stm32: introduce clocks for STM32MP21 platform dt-bindings: stm32: add STM32MP21 clocks and reset bindings
4 parents f0fd248 + 1803012 + 4bf2d27 + 0997607 commit b91217d

18 files changed

Lines changed: 3106 additions & 91 deletions

File tree

‎Documentation/devicetree/bindings/clock/st,stm32mp21-rcc.yaml‎

Lines changed: 199 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,199 @@
1+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2+
%YAML 1.2
3+
---
4+
$id: http://devicetree.org/schemas/clock/st,stm32mp21-rcc.yaml#
5+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6+
7+
title: STM32MP21 Reset Clock Controller
8+
9+
maintainers:
10+
- Gabriel Fernandez <gabriel.fernandez@foss.st.com>
11+
12+
description: |
13+
The RCC hardware block is both a reset and a clock controller.
14+
RCC makes also power management (resume/suspend).
15+
16+
See also:
17+
include/dt-bindings/clock/st,stm32mp21-rcc.h
18+
include/dt-bindings/reset/st,stm32mp21-rcc.h
19+
20+
properties:
21+
compatible:
22+
enum:
23+
- st,stm32mp21-rcc
24+
25+
reg:
26+
maxItems: 1
27+
28+
'#clock-cells':
29+
const: 1
30+
31+
'#reset-cells':
32+
const: 1
33+
34+
clocks:
35+
items:
36+
- description: CK_SCMI_HSE High Speed External oscillator (8 to 48 MHz)
37+
- description: CK_SCMI_HSI High Speed Internal oscillator (~ 64 MHz)
38+
- description: CK_SCMI_MSI Low Power Internal oscillator (~ 4 MHz or ~ 16 MHz)
39+
- description: CK_SCMI_LSE Low Speed External oscillator (32 KHz)
40+
- description: CK_SCMI_LSI Low Speed Internal oscillator (~ 32 KHz)
41+
- description: CK_SCMI_HSE_DIV2 CK_SCMI_HSE divided by 2 (could be gated)
42+
- description: CK_SCMI_ICN_HS_MCU High Speed interconnect bus clock
43+
- description: CK_SCMI_ICN_LS_MCU Low Speed interconnect bus clock
44+
- description: CK_SCMI_ICN_SDMMC SDMMC interconnect bus clock
45+
- description: CK_SCMI_ICN_DDR DDR interconnect bus clock
46+
- description: CK_SCMI_ICN_DISPLAY Display interconnect bus clock
47+
- description: CK_SCMI_ICN_HSL HSL interconnect bus clock
48+
- description: CK_SCMI_ICN_NIC NIC interconnect bus clock
49+
- description: CK_SCMI_FLEXGEN_07 flexgen clock 7
50+
- description: CK_SCMI_FLEXGEN_08 flexgen clock 8
51+
- description: CK_SCMI_FLEXGEN_09 flexgen clock 9
52+
- description: CK_SCMI_FLEXGEN_10 flexgen clock 10
53+
- description: CK_SCMI_FLEXGEN_11 flexgen clock 11
54+
- description: CK_SCMI_FLEXGEN_12 flexgen clock 12
55+
- description: CK_SCMI_FLEXGEN_13 flexgen clock 13
56+
- description: CK_SCMI_FLEXGEN_14 flexgen clock 14
57+
- description: CK_SCMI_FLEXGEN_16 flexgen clock 16
58+
- description: CK_SCMI_FLEXGEN_17 flexgen clock 17
59+
- description: CK_SCMI_FLEXGEN_18 flexgen clock 18
60+
- description: CK_SCMI_FLEXGEN_19 flexgen clock 19
61+
- description: CK_SCMI_FLEXGEN_20 flexgen clock 20
62+
- description: CK_SCMI_FLEXGEN_21 flexgen clock 21
63+
- description: CK_SCMI_FLEXGEN_22 flexgen clock 22
64+
- description: CK_SCMI_FLEXGEN_23 flexgen clock 23
65+
- description: CK_SCMI_FLEXGEN_24 flexgen clock 24
66+
- description: CK_SCMI_FLEXGEN_25 flexgen clock 25
67+
- description: CK_SCMI_FLEXGEN_26 flexgen clock 26
68+
- description: CK_SCMI_FLEXGEN_27 flexgen clock 27
69+
- description: CK_SCMI_FLEXGEN_29 flexgen clock 29
70+
- description: CK_SCMI_FLEXGEN_30 flexgen clock 30
71+
- description: CK_SCMI_FLEXGEN_31 flexgen clock 31
72+
- description: CK_SCMI_FLEXGEN_33 flexgen clock 33
73+
- description: CK_SCMI_FLEXGEN_36 flexgen clock 36
74+
- description: CK_SCMI_FLEXGEN_37 flexgen clock 37
75+
- description: CK_SCMI_FLEXGEN_38 flexgen clock 38
76+
- description: CK_SCMI_FLEXGEN_39 flexgen clock 39
77+
- description: CK_SCMI_FLEXGEN_40 flexgen clock 40
78+
- description: CK_SCMI_FLEXGEN_41 flexgen clock 41
79+
- description: CK_SCMI_FLEXGEN_42 flexgen clock 42
80+
- description: CK_SCMI_FLEXGEN_43 flexgen clock 43
81+
- description: CK_SCMI_FLEXGEN_44 flexgen clock 44
82+
- description: CK_SCMI_FLEXGEN_45 flexgen clock 45
83+
- description: CK_SCMI_FLEXGEN_46 flexgen clock 46
84+
- description: CK_SCMI_FLEXGEN_47 flexgen clock 47
85+
- description: CK_SCMI_FLEXGEN_48 flexgen clock 48
86+
- description: CK_SCMI_FLEXGEN_50 flexgen clock 50
87+
- description: CK_SCMI_FLEXGEN_51 flexgen clock 51
88+
- description: CK_SCMI_FLEXGEN_52 flexgen clock 52
89+
- description: CK_SCMI_FLEXGEN_53 flexgen clock 53
90+
- description: CK_SCMI_FLEXGEN_54 flexgen clock 54
91+
- description: CK_SCMI_FLEXGEN_55 flexgen clock 55
92+
- description: CK_SCMI_FLEXGEN_56 flexgen clock 56
93+
- description: CK_SCMI_FLEXGEN_57 flexgen clock 57
94+
- description: CK_SCMI_FLEXGEN_58 flexgen clock 58
95+
- description: CK_SCMI_FLEXGEN_61 flexgen clock 61
96+
- description: CK_SCMI_FLEXGEN_62 flexgen clock 62
97+
- description: CK_SCMI_FLEXGEN_63 flexgen clock 63
98+
- description: CK_SCMI_ICN_APB1 Peripheral bridge 1
99+
- description: CK_SCMI_ICN_APB2 Peripheral bridge 2
100+
- description: CK_SCMI_ICN_APB3 Peripheral bridge 3
101+
- description: CK_SCMI_ICN_APB4 Peripheral bridge 4
102+
- description: CK_SCMI_ICN_APB5 Peripheral bridge 5
103+
- description: CK_SCMI_ICN_APBDBG Peripheral bridge for debug
104+
- description: CK_SCMI_TIMG1 Peripheral bridge for timer1
105+
- description: CK_SCMI_TIMG2 Peripheral bridge for timer2
106+
107+
access-controllers:
108+
maxItems: 1
109+
110+
required:
111+
- compatible
112+
- reg
113+
- '#clock-cells'
114+
- '#reset-cells'
115+
- clocks
116+
117+
additionalProperties: false
118+
119+
examples:
120+
- |
121+
#include <dt-bindings/clock/st,stm32mp21-rcc.h>
122+
123+
clock-controller@44200000 {
124+
compatible = "st,stm32mp21-rcc";
125+
reg = <0x44200000 0x10000>;
126+
#clock-cells = <1>;
127+
#reset-cells = <1>;
128+
clocks = <&scmi_clk CK_SCMI_HSE>,
129+
<&scmi_clk CK_SCMI_HSI>,
130+
<&scmi_clk CK_SCMI_MSI>,
131+
<&scmi_clk CK_SCMI_LSE>,
132+
<&scmi_clk CK_SCMI_LSI>,
133+
<&scmi_clk CK_SCMI_HSE_DIV2>,
134+
<&scmi_clk CK_SCMI_ICN_HS_MCU>,
135+
<&scmi_clk CK_SCMI_ICN_LS_MCU>,
136+
<&scmi_clk CK_SCMI_ICN_SDMMC>,
137+
<&scmi_clk CK_SCMI_ICN_DDR>,
138+
<&scmi_clk CK_SCMI_ICN_DISPLAY>,
139+
<&scmi_clk CK_SCMI_ICN_HSL>,
140+
<&scmi_clk CK_SCMI_ICN_NIC>,
141+
<&scmi_clk CK_SCMI_FLEXGEN_07>,
142+
<&scmi_clk CK_SCMI_FLEXGEN_08>,
143+
<&scmi_clk CK_SCMI_FLEXGEN_09>,
144+
<&scmi_clk CK_SCMI_FLEXGEN_10>,
145+
<&scmi_clk CK_SCMI_FLEXGEN_11>,
146+
<&scmi_clk CK_SCMI_FLEXGEN_12>,
147+
<&scmi_clk CK_SCMI_FLEXGEN_13>,
148+
<&scmi_clk CK_SCMI_FLEXGEN_14>,
149+
<&scmi_clk CK_SCMI_FLEXGEN_16>,
150+
<&scmi_clk CK_SCMI_FLEXGEN_17>,
151+
<&scmi_clk CK_SCMI_FLEXGEN_18>,
152+
<&scmi_clk CK_SCMI_FLEXGEN_19>,
153+
<&scmi_clk CK_SCMI_FLEXGEN_20>,
154+
<&scmi_clk CK_SCMI_FLEXGEN_21>,
155+
<&scmi_clk CK_SCMI_FLEXGEN_22>,
156+
<&scmi_clk CK_SCMI_FLEXGEN_23>,
157+
<&scmi_clk CK_SCMI_FLEXGEN_24>,
158+
<&scmi_clk CK_SCMI_FLEXGEN_25>,
159+
<&scmi_clk CK_SCMI_FLEXGEN_26>,
160+
<&scmi_clk CK_SCMI_FLEXGEN_27>,
161+
<&scmi_clk CK_SCMI_FLEXGEN_29>,
162+
<&scmi_clk CK_SCMI_FLEXGEN_30>,
163+
<&scmi_clk CK_SCMI_FLEXGEN_31>,
164+
<&scmi_clk CK_SCMI_FLEXGEN_33>,
165+
<&scmi_clk CK_SCMI_FLEXGEN_36>,
166+
<&scmi_clk CK_SCMI_FLEXGEN_37>,
167+
<&scmi_clk CK_SCMI_FLEXGEN_38>,
168+
<&scmi_clk CK_SCMI_FLEXGEN_39>,
169+
<&scmi_clk CK_SCMI_FLEXGEN_40>,
170+
<&scmi_clk CK_SCMI_FLEXGEN_41>,
171+
<&scmi_clk CK_SCMI_FLEXGEN_42>,
172+
<&scmi_clk CK_SCMI_FLEXGEN_43>,
173+
<&scmi_clk CK_SCMI_FLEXGEN_44>,
174+
<&scmi_clk CK_SCMI_FLEXGEN_45>,
175+
<&scmi_clk CK_SCMI_FLEXGEN_46>,
176+
<&scmi_clk CK_SCMI_FLEXGEN_47>,
177+
<&scmi_clk CK_SCMI_FLEXGEN_48>,
178+
<&scmi_clk CK_SCMI_FLEXGEN_50>,
179+
<&scmi_clk CK_SCMI_FLEXGEN_51>,
180+
<&scmi_clk CK_SCMI_FLEXGEN_52>,
181+
<&scmi_clk CK_SCMI_FLEXGEN_53>,
182+
<&scmi_clk CK_SCMI_FLEXGEN_54>,
183+
<&scmi_clk CK_SCMI_FLEXGEN_55>,
184+
<&scmi_clk CK_SCMI_FLEXGEN_56>,
185+
<&scmi_clk CK_SCMI_FLEXGEN_57>,
186+
<&scmi_clk CK_SCMI_FLEXGEN_58>,
187+
<&scmi_clk CK_SCMI_FLEXGEN_61>,
188+
<&scmi_clk CK_SCMI_FLEXGEN_62>,
189+
<&scmi_clk CK_SCMI_FLEXGEN_63>,
190+
<&scmi_clk CK_SCMI_ICN_APB1>,
191+
<&scmi_clk CK_SCMI_ICN_APB2>,
192+
<&scmi_clk CK_SCMI_ICN_APB3>,
193+
<&scmi_clk CK_SCMI_ICN_APB4>,
194+
<&scmi_clk CK_SCMI_ICN_APB5>,
195+
<&scmi_clk CK_SCMI_ICN_APBDBG>,
196+
<&scmi_clk CK_SCMI_TIMG1>,
197+
<&scmi_clk CK_SCMI_TIMG2>;
198+
};
199+
...

‎Documentation/devicetree/bindings/clock/st,stm32mp25-rcc.yaml‎

Lines changed: 6 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -11,9 +11,9 @@ maintainers:
1111

1212
description: |
1313
The RCC hardware block is both a reset and a clock controller.
14-
RCC makes also power management (resume/supend).
14+
RCC makes also power management (resume/suspend).
1515
16-
See also::
16+
See also:
1717
include/dt-bindings/clock/st,stm32mp25-rcc.h
1818
include/dt-bindings/reset/st,stm32mp25-rcc.h
1919
@@ -38,7 +38,7 @@ properties:
3838
- description: CK_SCMI_MSI Low Power Internal oscillator (~ 4 MHz or ~ 16 MHz)
3939
- description: CK_SCMI_LSE Low Speed External oscillator (32 KHz)
4040
- description: CK_SCMI_LSI Low Speed Internal oscillator (~ 32 KHz)
41-
- description: CK_SCMI_HSE_DIV2 CK_SCMI_HSE divided by 2 (coud be gated)
41+
- description: CK_SCMI_HSE_DIV2 CK_SCMI_HSE divided by 2 (could be gated)
4242
- description: CK_SCMI_ICN_HS_MCU High Speed interconnect bus clock
4343
- description: CK_SCMI_ICN_LS_MCU Low Speed interconnect bus clock
4444
- description: CK_SCMI_ICN_SDMMC SDMMC interconnect bus clock
@@ -108,15 +108,14 @@ properties:
108108
- description: CK_SCMI_ICN_APB2 Peripheral bridge 2
109109
- description: CK_SCMI_ICN_APB3 Peripheral bridge 3
110110
- description: CK_SCMI_ICN_APB4 Peripheral bridge 4
111-
- description: CK_SCMI_ICN_APBDBG Peripheral bridge for degub
111+
- description: CK_SCMI_ICN_APBDBG Peripheral bridge for debug
112112
- description: CK_SCMI_TIMG1 Peripheral bridge for timer1
113113
- description: CK_SCMI_TIMG2 Peripheral bridge for timer2
114114
- description: CK_SCMI_PLL3 PLL3 clock
115115
- description: clk_dsi_txbyte DSI byte clock
116116

117117
access-controllers:
118-
minItems: 1
119-
maxItems: 2
118+
maxItems: 1
120119

121120
required:
122121
- compatible
@@ -131,7 +130,7 @@ examples:
131130
- |
132131
#include <dt-bindings/clock/st,stm32mp25-rcc.h>
133132
134-
rcc: clock-controller@44200000 {
133+
clock-controller@44200000 {
135134
compatible = "st,stm32mp25-rcc";
136135
reg = <0x44200000 0x10000>;
137136
#clock-cells = <1>;

‎arch/arm/mach-at91/pm_suspend.S‎

Lines changed: 7 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -689,6 +689,10 @@ sr_dis_exit:
689689
bic tmp2, tmp2, #AT91_PMC_PLL_UPDT_ID
690690
str tmp2, [pmc, #AT91_PMC_PLL_UPDT]
691691

692+
/* save acr */
693+
ldr tmp2, [pmc, #AT91_PMC_PLL_ACR]
694+
str tmp2, .saved_acr
695+
692696
/* save div. */
693697
mov tmp1, #0
694698
ldr tmp2, [pmc, #AT91_PMC_PLL_CTRL0]
@@ -758,7 +762,7 @@ sr_dis_exit:
758762
str tmp1, [pmc, #AT91_PMC_PLL_UPDT]
759763

760764
/* step 2. */
761-
ldr tmp1, =AT91_PMC_PLL_ACR_DEFAULT_PLLA
765+
ldr tmp1, .saved_acr
762766
str tmp1, [pmc, #AT91_PMC_PLL_ACR]
763767

764768
/* step 3. */
@@ -1207,6 +1211,8 @@ ENDPROC(at91_pm_suspend_in_sram)
12071211
#endif
12081212
.saved_mckr:
12091213
.word 0
1214+
.saved_acr:
1215+
.word 0
12101216
.saved_pllar:
12111217
.word 0
12121218
.saved_sam9_lpr:

‎drivers/clk/at91/clk-master.c‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -580,6 +580,9 @@ clk_sama7g5_master_recalc_rate(struct clk_hw *hw,
580580
{
581581
struct clk_master *master = to_clk_master(hw);
582582

583+
if (master->div == MASTER_PRES_MAX)
584+
return DIV_ROUND_CLOSEST_ULL(parent_rate, 3);
585+
583586
return DIV_ROUND_CLOSEST_ULL(parent_rate, (1 << master->div));
584587
}
585588

0 commit comments

Comments
 (0)