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Lanik123andersson
Lanik123
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clk: qcom: gcc: Add support for Global Clock controller found on MSM8940
Modify existing MSM8917 driver to support MSM8940 SoC. MSM8940 SoC has the same changes as MSM8937 SoC, but with additional IPA clk and different GFX3D clock frequency table. Signed-off-by: Daniil Titov <daniilt971@gmail.com> Signed-off-by: Barnabás Czémán <barnabas.czeman@mainlining.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20251117-gcc-msm8940-sdm439-v2-2-4af57c8bc7eb@mainlining.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
1 parent d88d5be commit b97a615

2 files changed

Lines changed: 234 additions & 3 deletions

File tree

‎drivers/clk/qcom/Kconfig‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -387,12 +387,12 @@ config MSM_GCC_8916
387387
SD/eMMC, display, graphics, camera etc.
388388

389389
config MSM_GCC_8917
390-
tristate "MSM89(17/37)/QM215 Global Clock Controller"
390+
tristate "MSM89(17/37/40)/QM215 Global Clock Controller"
391391
depends on ARM64 || COMPILE_TEST
392392
select QCOM_GDSC
393393
help
394-
Support for the global clock controller on msm8917, msm8937
395-
and qm215 devices.
394+
Support for the global clock controller on msm8917, msm8937,
395+
msm8940 and qm215 devices.
396396
Say Y if you want to use devices such as UART, SPI i2c, USB,
397397
SD/eMMC, display, graphics, camera etc.
398398

‎drivers/clk/qcom/gcc-msm8917.c‎

Lines changed: 231 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -957,6 +957,27 @@ static const struct freq_tbl ftbl_gfx3d_clk_src_msm8937[] = {
957957
{ }
958958
};
959959

960+
static const struct freq_tbl ftbl_gfx3d_clk_src_msm8940[] = {
961+
F(19200000, P_XO, 1, 0, 0),
962+
F(50000000, P_GPLL0, 16, 0, 0),
963+
F(80000000, P_GPLL0, 10, 0, 0),
964+
F(100000000, P_GPLL0, 8, 0, 0),
965+
F(160000000, P_GPLL0, 5, 0, 0),
966+
F(200000000, P_GPLL0, 4, 0, 0),
967+
F(216000000, P_GPLL6, 5, 0, 0),
968+
F(228570000, P_GPLL0, 3.5, 0, 0),
969+
F(240000000, P_GPLL6, 4.5, 0, 0),
970+
F(266670000, P_GPLL0, 3, 0, 0),
971+
F(300000000, P_GPLL3, 1, 0, 0),
972+
F(320000000, P_GPLL0, 2.5, 0, 0),
973+
F(375000000, P_GPLL3, 1, 0, 0),
974+
F(400000000, P_GPLL0, 2, 0, 0),
975+
F(450000000, P_GPLL3, 1, 0, 0),
976+
F(475000000, P_GPLL3, 1, 0, 0),
977+
F(500000000, P_GPLL3, 1, 0, 0),
978+
{ }
979+
};
980+
960981
static struct clk_rcg2 gfx3d_clk_src = {
961982
.cmd_rcgr = 0x59000,
962983
.hid_width = 5,
@@ -3307,6 +3328,19 @@ static struct clk_branch gcc_vfe_tbu_clk = {
33073328
}
33083329
};
33093330

3331+
static struct clk_branch gcc_ipa_tbu_clk = {
3332+
.halt_reg = 0x120a0,
3333+
.halt_check = BRANCH_VOTED,
3334+
.clkr = {
3335+
.enable_reg = 0x4500c,
3336+
.enable_mask = BIT(16),
3337+
.hw.init = &(struct clk_init_data){
3338+
.name = "gcc_ipa_tbu_clk",
3339+
.ops = &clk_branch2_ops,
3340+
},
3341+
},
3342+
};
3343+
33103344
static struct gdsc venus_gdsc = {
33113345
.gdscr = 0x4c018,
33123346
.cxcs = (unsigned int []){ 0x4c024, 0x4c01c },
@@ -3764,6 +3798,189 @@ static struct clk_regmap *gcc_msm8937_clocks[] = {
37643798
[GCC_VFE_TBU_CLK] = &gcc_vfe_tbu_clk.clkr,
37653799
};
37663800

3801+
static struct clk_regmap *gcc_msm8940_clocks[] = {
3802+
[GPLL0] = &gpll0.clkr,
3803+
[GPLL0_EARLY] = &gpll0_early.clkr,
3804+
[GPLL0_SLEEP_CLK_SRC] = &gpll0_sleep_clk_src.clkr,
3805+
[GPLL3] = &gpll3.clkr,
3806+
[GPLL3_EARLY] = &gpll3_early.clkr,
3807+
[GPLL4] = &gpll4.clkr,
3808+
[GPLL4_EARLY] = &gpll4_early.clkr,
3809+
[GPLL6] = &gpll6,
3810+
[GPLL6_EARLY] = &gpll6_early.clkr,
3811+
[APSS_AHB_CLK_SRC] = &apss_ahb_clk_src.clkr,
3812+
[MSM8937_BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
3813+
[MSM8937_BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
3814+
[BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
3815+
[BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
3816+
[BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
3817+
[BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
3818+
[BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
3819+
[BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
3820+
[BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
3821+
[BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
3822+
[BLSP2_QUP1_I2C_APPS_CLK_SRC] = &blsp2_qup1_i2c_apps_clk_src.clkr,
3823+
[BLSP2_QUP1_SPI_APPS_CLK_SRC] = &blsp2_qup1_spi_apps_clk_src.clkr,
3824+
[BLSP2_QUP2_I2C_APPS_CLK_SRC] = &blsp2_qup2_i2c_apps_clk_src.clkr,
3825+
[BLSP2_QUP2_SPI_APPS_CLK_SRC] = &blsp2_qup2_spi_apps_clk_src.clkr,
3826+
[BLSP2_QUP3_I2C_APPS_CLK_SRC] = &blsp2_qup3_i2c_apps_clk_src.clkr,
3827+
[BLSP2_QUP3_SPI_APPS_CLK_SRC] = &blsp2_qup3_spi_apps_clk_src.clkr,
3828+
[MSM8937_BLSP2_QUP4_I2C_APPS_CLK_SRC] = &blsp2_qup4_i2c_apps_clk_src.clkr,
3829+
[MSM8937_BLSP2_QUP4_SPI_APPS_CLK_SRC] = &blsp2_qup4_spi_apps_clk_src.clkr,
3830+
[BLSP2_UART1_APPS_CLK_SRC] = &blsp2_uart1_apps_clk_src.clkr,
3831+
[BLSP2_UART2_APPS_CLK_SRC] = &blsp2_uart2_apps_clk_src.clkr,
3832+
[BYTE0_CLK_SRC] = &byte0_clk_src.clkr,
3833+
[MSM8937_BYTE1_CLK_SRC] = &byte1_clk_src.clkr,
3834+
[CAMSS_GP0_CLK_SRC] = &camss_gp0_clk_src.clkr,
3835+
[CAMSS_GP1_CLK_SRC] = &camss_gp1_clk_src.clkr,
3836+
[CAMSS_TOP_AHB_CLK_SRC] = &camss_top_ahb_clk_src.clkr,
3837+
[CCI_CLK_SRC] = &cci_clk_src.clkr,
3838+
[CPP_CLK_SRC] = &cpp_clk_src.clkr,
3839+
[CRYPTO_CLK_SRC] = &crypto_clk_src.clkr,
3840+
[CSI0PHYTIMER_CLK_SRC] = &csi0phytimer_clk_src.clkr,
3841+
[CSI0_CLK_SRC] = &csi0_clk_src.clkr,
3842+
[CSI1PHYTIMER_CLK_SRC] = &csi1phytimer_clk_src.clkr,
3843+
[CSI1_CLK_SRC] = &csi1_clk_src.clkr,
3844+
[CSI2_CLK_SRC] = &csi2_clk_src.clkr,
3845+
[ESC0_CLK_SRC] = &esc0_clk_src.clkr,
3846+
[MSM8937_ESC1_CLK_SRC] = &esc1_clk_src.clkr,
3847+
[GFX3D_CLK_SRC] = &gfx3d_clk_src.clkr,
3848+
[GP1_CLK_SRC] = &gp1_clk_src.clkr,
3849+
[GP2_CLK_SRC] = &gp2_clk_src.clkr,
3850+
[GP3_CLK_SRC] = &gp3_clk_src.clkr,
3851+
[JPEG0_CLK_SRC] = &jpeg0_clk_src.clkr,
3852+
[MCLK0_CLK_SRC] = &mclk0_clk_src.clkr,
3853+
[MCLK1_CLK_SRC] = &mclk1_clk_src.clkr,
3854+
[MCLK2_CLK_SRC] = &mclk2_clk_src.clkr,
3855+
[MDP_CLK_SRC] = &mdp_clk_src.clkr,
3856+
[PCLK0_CLK_SRC] = &pclk0_clk_src.clkr,
3857+
[MSM8937_PCLK1_CLK_SRC] = &pclk1_clk_src.clkr,
3858+
[PDM2_CLK_SRC] = &pdm2_clk_src.clkr,
3859+
[SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
3860+
[SDCC1_ICE_CORE_CLK_SRC] = &sdcc1_ice_core_clk_src.clkr,
3861+
[SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,
3862+
[USB_HS_SYSTEM_CLK_SRC] = &usb_hs_system_clk_src.clkr,
3863+
[VCODEC0_CLK_SRC] = &vcodec0_clk_src.clkr,
3864+
[VFE0_CLK_SRC] = &vfe0_clk_src.clkr,
3865+
[VFE1_CLK_SRC] = &vfe1_clk_src.clkr,
3866+
[VSYNC_CLK_SRC] = &vsync_clk_src.clkr,
3867+
[GCC_APSS_TCU_CLK] = &gcc_apss_tcu_clk.clkr,
3868+
[GCC_BIMC_GFX_CLK] = &gcc_bimc_gfx_clk.clkr,
3869+
[GCC_BIMC_GPU_CLK] = &gcc_bimc_gpu_clk.clkr,
3870+
[GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
3871+
[MSM8937_GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
3872+
[MSM8937_GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
3873+
[GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
3874+
[GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
3875+
[GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
3876+
[GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
3877+
[GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
3878+
[GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
3879+
[GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
3880+
[GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
3881+
[GCC_BLSP2_AHB_CLK] = &gcc_blsp2_ahb_clk.clkr,
3882+
[GCC_BLSP2_QUP1_I2C_APPS_CLK] = &gcc_blsp2_qup1_i2c_apps_clk.clkr,
3883+
[GCC_BLSP2_QUP1_SPI_APPS_CLK] = &gcc_blsp2_qup1_spi_apps_clk.clkr,
3884+
[GCC_BLSP2_QUP2_I2C_APPS_CLK] = &gcc_blsp2_qup2_i2c_apps_clk.clkr,
3885+
[GCC_BLSP2_QUP2_SPI_APPS_CLK] = &gcc_blsp2_qup2_spi_apps_clk.clkr,
3886+
[GCC_BLSP2_QUP3_I2C_APPS_CLK] = &gcc_blsp2_qup3_i2c_apps_clk.clkr,
3887+
[GCC_BLSP2_QUP3_SPI_APPS_CLK] = &gcc_blsp2_qup3_spi_apps_clk.clkr,
3888+
[MSM8937_GCC_BLSP2_QUP4_I2C_APPS_CLK] = &gcc_blsp2_qup4_i2c_apps_clk.clkr,
3889+
[MSM8937_GCC_BLSP2_QUP4_SPI_APPS_CLK] = &gcc_blsp2_qup4_spi_apps_clk.clkr,
3890+
[GCC_BLSP2_UART1_APPS_CLK] = &gcc_blsp2_uart1_apps_clk.clkr,
3891+
[GCC_BLSP2_UART2_APPS_CLK] = &gcc_blsp2_uart2_apps_clk.clkr,
3892+
[GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
3893+
[GCC_CAMSS_AHB_CLK] = &gcc_camss_ahb_clk.clkr,
3894+
[GCC_CAMSS_CCI_AHB_CLK] = &gcc_camss_cci_ahb_clk.clkr,
3895+
[GCC_CAMSS_CCI_CLK] = &gcc_camss_cci_clk.clkr,
3896+
[GCC_CAMSS_CPP_AHB_CLK] = &gcc_camss_cpp_ahb_clk.clkr,
3897+
[GCC_CAMSS_CPP_CLK] = &gcc_camss_cpp_clk.clkr,
3898+
[GCC_CAMSS_CSI0PHYTIMER_CLK] = &gcc_camss_csi0phytimer_clk.clkr,
3899+
[GCC_CAMSS_CSI0PHY_CLK] = &gcc_camss_csi0phy_clk.clkr,
3900+
[GCC_CAMSS_CSI0PIX_CLK] = &gcc_camss_csi0pix_clk.clkr,
3901+
[GCC_CAMSS_CSI0RDI_CLK] = &gcc_camss_csi0rdi_clk.clkr,
3902+
[GCC_CAMSS_CSI0_AHB_CLK] = &gcc_camss_csi0_ahb_clk.clkr,
3903+
[GCC_CAMSS_CSI0_CLK] = &gcc_camss_csi0_clk.clkr,
3904+
[GCC_CAMSS_CSI1PHYTIMER_CLK] = &gcc_camss_csi1phytimer_clk.clkr,
3905+
[GCC_CAMSS_CSI1PHY_CLK] = &gcc_camss_csi1phy_clk.clkr,
3906+
[GCC_CAMSS_CSI1PIX_CLK] = &gcc_camss_csi1pix_clk.clkr,
3907+
[GCC_CAMSS_CSI1RDI_CLK] = &gcc_camss_csi1rdi_clk.clkr,
3908+
[GCC_CAMSS_CSI1_AHB_CLK] = &gcc_camss_csi1_ahb_clk.clkr,
3909+
[GCC_CAMSS_CSI1_CLK] = &gcc_camss_csi1_clk.clkr,
3910+
[GCC_CAMSS_CSI2PHY_CLK] = &gcc_camss_csi2phy_clk.clkr,
3911+
[GCC_CAMSS_CSI2PIX_CLK] = &gcc_camss_csi2pix_clk.clkr,
3912+
[GCC_CAMSS_CSI2RDI_CLK] = &gcc_camss_csi2rdi_clk.clkr,
3913+
[GCC_CAMSS_CSI2_AHB_CLK] = &gcc_camss_csi2_ahb_clk.clkr,
3914+
[GCC_CAMSS_CSI2_CLK] = &gcc_camss_csi2_clk.clkr,
3915+
[GCC_CAMSS_CSI_VFE0_CLK] = &gcc_camss_csi_vfe0_clk.clkr,
3916+
[GCC_CAMSS_CSI_VFE1_CLK] = &gcc_camss_csi_vfe1_clk.clkr,
3917+
[GCC_CAMSS_GP0_CLK] = &gcc_camss_gp0_clk.clkr,
3918+
[GCC_CAMSS_GP1_CLK] = &gcc_camss_gp1_clk.clkr,
3919+
[GCC_CAMSS_ISPIF_AHB_CLK] = &gcc_camss_ispif_ahb_clk.clkr,
3920+
[GCC_CAMSS_JPEG0_CLK] = &gcc_camss_jpeg0_clk.clkr,
3921+
[GCC_CAMSS_JPEG_AHB_CLK] = &gcc_camss_jpeg_ahb_clk.clkr,
3922+
[GCC_CAMSS_JPEG_AXI_CLK] = &gcc_camss_jpeg_axi_clk.clkr,
3923+
[GCC_CAMSS_MCLK0_CLK] = &gcc_camss_mclk0_clk.clkr,
3924+
[GCC_CAMSS_MCLK1_CLK] = &gcc_camss_mclk1_clk.clkr,
3925+
[GCC_CAMSS_MCLK2_CLK] = &gcc_camss_mclk2_clk.clkr,
3926+
[GCC_CAMSS_MICRO_AHB_CLK] = &gcc_camss_micro_ahb_clk.clkr,
3927+
[GCC_CAMSS_TOP_AHB_CLK] = &gcc_camss_top_ahb_clk.clkr,
3928+
[GCC_CAMSS_VFE0_AHB_CLK] = &gcc_camss_vfe0_ahb_clk.clkr,
3929+
[GCC_CAMSS_VFE0_AXI_CLK] = &gcc_camss_vfe0_axi_clk.clkr,
3930+
[GCC_CAMSS_VFE0_CLK] = &gcc_camss_vfe0_clk.clkr,
3931+
[GCC_CAMSS_VFE1_AHB_CLK] = &gcc_camss_vfe1_ahb_clk.clkr,
3932+
[GCC_CAMSS_VFE1_AXI_CLK] = &gcc_camss_vfe1_axi_clk.clkr,
3933+
[GCC_CAMSS_VFE1_CLK] = &gcc_camss_vfe1_clk.clkr,
3934+
[GCC_CPP_TBU_CLK] = &gcc_cpp_tbu_clk.clkr,
3935+
[GCC_CRYPTO_AHB_CLK] = &gcc_crypto_ahb_clk.clkr,
3936+
[GCC_CRYPTO_AXI_CLK] = &gcc_crypto_axi_clk.clkr,
3937+
[GCC_CRYPTO_CLK] = &gcc_crypto_clk.clkr,
3938+
[GCC_DCC_CLK] = &gcc_dcc_clk.clkr,
3939+
[GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
3940+
[GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
3941+
[GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
3942+
[GCC_JPEG_TBU_CLK] = &gcc_jpeg_tbu_clk.clkr,
3943+
[GCC_MDP_TBU_CLK] = &gcc_mdp_tbu_clk.clkr,
3944+
[GCC_MDSS_AHB_CLK] = &gcc_mdss_ahb_clk.clkr,
3945+
[GCC_MDSS_AXI_CLK] = &gcc_mdss_axi_clk.clkr,
3946+
[GCC_MDSS_BYTE0_CLK] = &gcc_mdss_byte0_clk.clkr,
3947+
[MSM8937_GCC_MDSS_BYTE1_CLK] = &gcc_mdss_byte1_clk.clkr,
3948+
[GCC_MDSS_ESC0_CLK] = &gcc_mdss_esc0_clk.clkr,
3949+
[MSM8937_GCC_MDSS_ESC1_CLK] = &gcc_mdss_esc1_clk.clkr,
3950+
[GCC_MDSS_MDP_CLK] = &gcc_mdss_mdp_clk.clkr,
3951+
[GCC_MDSS_PCLK0_CLK] = &gcc_mdss_pclk0_clk.clkr,
3952+
[MSM8937_GCC_MDSS_PCLK1_CLK] = &gcc_mdss_pclk1_clk.clkr,
3953+
[GCC_MDSS_VSYNC_CLK] = &gcc_mdss_vsync_clk.clkr,
3954+
[GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr,
3955+
[GCC_MSS_Q6_BIMC_AXI_CLK] = &gcc_mss_q6_bimc_axi_clk.clkr,
3956+
[GCC_OXILI_AHB_CLK] = &gcc_oxili_ahb_clk.clkr,
3957+
[MSM8937_GCC_OXILI_AON_CLK] = &gcc_oxili_aon_clk.clkr,
3958+
[GCC_OXILI_GFX3D_CLK] = &gcc_oxili_gfx3d_clk.clkr,
3959+
[MSM8937_GCC_OXILI_TIMER_CLK] = &gcc_oxili_timer_clk.clkr,
3960+
[GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
3961+
[GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
3962+
[GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
3963+
[GCC_QDSS_DAP_CLK] = &gcc_qdss_dap_clk.clkr,
3964+
[GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
3965+
[GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
3966+
[GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr,
3967+
[GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
3968+
[GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
3969+
[GCC_SMMU_CFG_CLK] = &gcc_smmu_cfg_clk.clkr,
3970+
[GCC_USB2A_PHY_SLEEP_CLK] = &gcc_usb2a_phy_sleep_clk.clkr,
3971+
[GCC_USB_HS_AHB_CLK] = &gcc_usb_hs_ahb_clk.clkr,
3972+
[GCC_USB_HS_PHY_CFG_AHB_CLK] = &gcc_usb_hs_phy_cfg_ahb_clk.clkr,
3973+
[GCC_USB_HS_SYSTEM_CLK] = &gcc_usb_hs_system_clk.clkr,
3974+
[GCC_VENUS0_AHB_CLK] = &gcc_venus0_ahb_clk.clkr,
3975+
[GCC_VENUS0_AXI_CLK] = &gcc_venus0_axi_clk.clkr,
3976+
[GCC_VENUS0_CORE0_VCODEC0_CLK] = &gcc_venus0_core0_vcodec0_clk.clkr,
3977+
[GCC_VENUS0_VCODEC0_CLK] = &gcc_venus0_vcodec0_clk.clkr,
3978+
[GCC_VENUS_TBU_CLK] = &gcc_venus_tbu_clk.clkr,
3979+
[GCC_VFE1_TBU_CLK] = &gcc_vfe1_tbu_clk.clkr,
3980+
[GCC_VFE_TBU_CLK] = &gcc_vfe_tbu_clk.clkr,
3981+
[MSM8940_GCC_IPA_TBU_CLK] = &gcc_ipa_tbu_clk.clkr,
3982+
};
3983+
37673984
static const struct qcom_reset_map gcc_msm8917_resets[] = {
37683985
[GCC_CAMSS_MICRO_BCR] = { 0x56008 },
37693986
[GCC_MSS_BCR] = { 0x71000 },
@@ -3834,6 +4051,16 @@ static const struct qcom_cc_desc gcc_msm8937_desc = {
38344051
.num_gdscs = ARRAY_SIZE(gcc_msm8937_gdscs),
38354052
};
38364053

4054+
static const struct qcom_cc_desc gcc_msm8940_desc = {
4055+
.config = &gcc_msm8917_regmap_config,
4056+
.clks = gcc_msm8940_clocks,
4057+
.num_clks = ARRAY_SIZE(gcc_msm8940_clocks),
4058+
.resets = gcc_msm8917_resets,
4059+
.num_resets = ARRAY_SIZE(gcc_msm8917_resets),
4060+
.gdscs = gcc_msm8937_gdscs,
4061+
.num_gdscs = ARRAY_SIZE(gcc_msm8937_gdscs),
4062+
};
4063+
38374064
static void msm8937_clock_override(void)
38384065
{
38394066
/* GPLL3 750MHz configuration */
@@ -3871,6 +4098,9 @@ static int gcc_msm8917_probe(struct platform_device *pdev)
38714098
} else if (gcc_desc == &gcc_msm8937_desc) {
38724099
msm8937_clock_override();
38734100
gfx3d_clk_src.freq_tbl = ftbl_gfx3d_clk_src_msm8937;
4101+
} else if (gcc_desc == &gcc_msm8940_desc) {
4102+
msm8937_clock_override();
4103+
gfx3d_clk_src.freq_tbl = ftbl_gfx3d_clk_src_msm8940;
38744104
}
38754105

38764106
regmap = qcom_cc_map(pdev, gcc_desc);
@@ -3886,6 +4116,7 @@ static const struct of_device_id gcc_msm8917_match_table[] = {
38864116
{ .compatible = "qcom,gcc-msm8917", .data = &gcc_msm8917_desc },
38874117
{ .compatible = "qcom,gcc-qm215", .data = &gcc_qm215_desc },
38884118
{ .compatible = "qcom,gcc-msm8937", .data = &gcc_msm8937_desc },
4119+
{ .compatible = "qcom,gcc-msm8940", .data = &gcc_msm8940_desc },
38894120
{},
38904121
};
38914122
MODULE_DEVICE_TABLE(of, gcc_msm8917_match_table);

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