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Merge tag 'riscv-dt-for-v6.6' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into soc/dt
RISC-V Devicetrees for v6.6 StarFive: There's only StarFive stuff this time around, starting with some bindings to get clock ID defines out of the binding headers. Getting these (and the syscon bindings) in unblocked a swathe of stuff sitting on the list. Added are: new clock controllers and sycons, ethernet support, thermal sensors, USB and PCIe PHYs, hwrng, mmc and a few more besides for the VisionFive v2. The original VisionFive and BeagleV Starlight got some the thermal sensor support too, as that is supported by the same driver. These changes make the board actually usable with something other than an initramfs. Overlay support by way of the -@ flag set during dtb building, is added also. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> * tag 'riscv-dt-for-v6.6' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux: (26 commits) riscv: dts: starfive: jh7110: Fix GMAC configuration riscv: dts: starfive - Add hwrng node for JH7110 SoC riscv: dts: starfive - Add crypto and DMA node for JH7110 riscv: dts: starfive: Add mmc nodes on VisionFive 2 board riscv: dts: starfive: enable DCDC1&ALDO4 node in axp15060 riscv: dts: starfive: Add QSPI controller node for StarFive JH7110 SoC riscv: dts: starfive: jh7110: add the node and pins configuration for tdm riscv: dts: starfive: jh7110: add dma controller node riscv: dts: starfive: Add spi node and pins configuration riscv: dts: starfive: Add USB dts node for JH7110 riscv: dts: starfive: Add USB and PCIe PHY nodes for JH7110 riscv: dts: starfive: jh7110: Add temperature sensor node and thermal-zones riscv: dts: starfive: jh7100: Add temperature sensor node and thermal-zones riscv: dts: starfive: visionfive 2: Add configuration of gmac and phy riscv: dts: starfive: jh7110: Add ethernet device nodes riscv: dts: starfive: jh7110: Add PLL clocks source in SYSCRG node riscv: dts: starfive: jh7110: Add syscon nodes riscv: dts: starfive: jh7110: Add STGCRG/ISPCRG/VOUTCRG nodes riscv: dts: starfive: jh7110: Add DVP and HDMI TX pixel external clocks dt-bindings: clock: Add StarFive JH7110 Video-Output clock and reset generator ... Link: https://lore.kernel.org/r/20230813-naturist-fragment-ac7d10c453ba@spud Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2 parents eeb751c + f331eb1 commit ba81791

15 files changed

Lines changed: 1433 additions & 4 deletions

‎Documentation/devicetree/bindings/clock/starfive,jh7110-ispcrg.yaml‎

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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/starfive,jh7110-ispcrg.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: StarFive JH7110 Image-Signal-Process Clock and Reset Generator
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maintainers:
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- Xingyu Wu <xingyu.wu@starfivetech.com>
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properties:
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compatible:
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const: starfive,jh7110-ispcrg
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reg:
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maxItems: 1
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clocks:
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items:
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- description: ISP Top core
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- description: ISP Top Axi
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- description: NOC ISP Bus
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- description: external DVP
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clock-names:
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items:
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- const: isp_top_core
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- const: isp_top_axi
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- const: noc_bus_isp_axi
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- const: dvp_clk
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resets:
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items:
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- description: ISP Top core
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- description: ISP Top Axi
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- description: NOC ISP Bus
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'#clock-cells':
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const: 1
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description:
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See <dt-bindings/clock/starfive,jh7110-crg.h> for valid indices.
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'#reset-cells':
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const: 1
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description:
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See <dt-bindings/reset/starfive,jh7110-crg.h> for valid indices.
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power-domains:
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maxItems: 1
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description:
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ISP domain power
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- resets
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- '#clock-cells'
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- '#reset-cells'
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- power-domains
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/starfive,jh7110-crg.h>
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#include <dt-bindings/power/starfive,jh7110-pmu.h>
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#include <dt-bindings/reset/starfive,jh7110-crg.h>
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ispcrg: clock-controller@19810000 {
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compatible = "starfive,jh7110-ispcrg";
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reg = <0x19810000 0x10000>;
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clocks = <&syscrg JH7110_SYSCLK_ISP_TOP_CORE>,
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<&syscrg JH7110_SYSCLK_ISP_TOP_AXI>,
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<&syscrg JH7110_SYSCLK_NOC_BUS_ISP_AXI>,
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<&dvp_clk>;
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clock-names = "isp_top_core", "isp_top_axi",
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"noc_bus_isp_axi", "dvp_clk";
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resets = <&syscrg JH7110_SYSRST_ISP_TOP>,
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<&syscrg JH7110_SYSRST_ISP_TOP_AXI>,
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<&syscrg JH7110_SYSRST_NOC_BUS_ISP_AXI>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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power-domains = <&pwrc JH7110_PD_ISP>;
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};

‎Documentation/devicetree/bindings/clock/starfive,jh7110-pll.yaml‎

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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/starfive,jh7110-pll.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: StarFive JH7110 PLL Clock Generator
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description:
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These PLLs are high speed, low jitter frequency synthesizers in the JH7110.
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Each PLL works in integer mode or fraction mode, with configuration
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registers in the sys syscon. So the PLLs node should be a child of
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SYS-SYSCON node.
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The formula for calculating frequency is
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Fvco = Fref * (NI + NF) / M / Q1
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maintainers:
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- Xingyu Wu <xingyu.wu@starfivetech.com>
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properties:
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compatible:
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const: starfive,jh7110-pll
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clocks:
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maxItems: 1
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description: Main Oscillator (24 MHz)
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'#clock-cells':
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const: 1
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description:
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See <dt-bindings/clock/starfive,jh7110-crg.h> for valid indices.
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required:
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- compatible
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- clocks
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- '#clock-cells'
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additionalProperties: false
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examples:
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- |
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clock-controller {
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compatible = "starfive,jh7110-pll";
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clocks = <&osc>;
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#clock-cells = <1>;
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};

‎Documentation/devicetree/bindings/clock/starfive,jh7110-stgcrg.yaml‎

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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/starfive,jh7110-stgcrg.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: StarFive JH7110 System-Top-Group Clock and Reset Generator
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maintainers:
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- Xingyu Wu <xingyu.wu@starfivetech.com>
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properties:
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compatible:
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const: starfive,jh7110-stgcrg
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reg:
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maxItems: 1
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clocks:
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items:
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- description: Main Oscillator (24 MHz)
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- description: HIFI4 core
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- description: STG AXI/AHB
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- description: USB (125 MHz)
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- description: CPU Bus
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- description: HIFI4 Axi
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- description: NOC STG Bus
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- description: APB Bus
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clock-names:
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items:
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- const: osc
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- const: hifi4_core
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- const: stg_axiahb
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- const: usb_125m
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- const: cpu_bus
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- const: hifi4_axi
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- const: nocstg_bus
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- const: apb_bus
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'#clock-cells':
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const: 1
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description:
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See <dt-bindings/clock/starfive,jh7110-crg.h> for valid indices.
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'#reset-cells':
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const: 1
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description:
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See <dt-bindings/reset/starfive,jh7110-crg.h> for valid indices.
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- '#clock-cells'
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- '#reset-cells'
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/starfive,jh7110-crg.h>
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stgcrg: clock-controller@10230000 {
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compatible = "starfive,jh7110-stgcrg";
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reg = <0x10230000 0x10000>;
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clocks = <&osc>,
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<&syscrg JH7110_SYSCLK_HIFI4_CORE>,
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<&syscrg JH7110_SYSCLK_STG_AXIAHB>,
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<&syscrg JH7110_SYSCLK_USB_125M>,
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<&syscrg JH7110_SYSCLK_CPU_BUS>,
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<&syscrg JH7110_SYSCLK_HIFI4_AXI>,
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<&syscrg JH7110_SYSCLK_NOCSTG_BUS>,
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<&syscrg JH7110_SYSCLK_APB_BUS>;
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clock-names = "osc", "hifi4_core",
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"stg_axiahb", "usb_125m",
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"cpu_bus", "hifi4_axi",
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"nocstg_bus", "apb_bus";
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#clock-cells = <1>;
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#reset-cells = <1>;
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};

‎Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml‎

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- description: External I2S RX left/right channel clock
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- description: External TDM clock
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- description: External audio master clock
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- description: PLL0
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- description: PLL1
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- description: PLL2
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- items:
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- description: Main Oscillator (24 MHz)
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- description: External I2S RX left/right channel clock
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- description: External TDM clock
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- description: External audio master clock
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- description: PLL0
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- description: PLL1
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- description: PLL2
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clock-names:
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oneOf:
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- const: i2srx_lrck_ext
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- const: tdm_ext
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- const: mclk_ext
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- const: pll0_out
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- const: pll1_out
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- const: pll2_out
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- items:
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- const: osc
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- const: i2srx_lrck_ext
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- const: tdm_ext
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- const: mclk_ext
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- const: pll0_out
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- const: pll1_out
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- const: pll2_out
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'#clock-cells':
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const: 1
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<&gmac1_rgmii_rxin>,
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<&i2stx_bclk_ext>, <&i2stx_lrck_ext>,
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<&i2srx_bclk_ext>, <&i2srx_lrck_ext>,
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<&tdm_ext>, <&mclk_ext>;
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<&tdm_ext>, <&mclk_ext>,
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<&pllclk 0>, <&pllclk 1>, <&pllclk 2>;
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clock-names = "osc", "gmac1_rmii_refin",
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"gmac1_rgmii_rxin",
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"i2stx_bclk_ext", "i2stx_lrck_ext",
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"i2srx_bclk_ext", "i2srx_lrck_ext",
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"tdm_ext", "mclk_ext";
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"tdm_ext", "mclk_ext",
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"pll0_out", "pll1_out", "pll2_out";
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#clock-cells = <1>;
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#reset-cells = <1>;
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};

‎Documentation/devicetree/bindings/clock/starfive,jh7110-voutcrg.yaml‎

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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/starfive,jh7110-voutcrg.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: StarFive JH7110 Video-Output Clock and Reset Generator
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maintainers:
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- Xingyu Wu <xingyu.wu@starfivetech.com>
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properties:
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compatible:
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const: starfive,jh7110-voutcrg
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reg:
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maxItems: 1
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clocks:
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items:
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- description: Vout Top core
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- description: Vout Top Ahb
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- description: Vout Top Axi
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- description: Vout Top HDMI MCLK
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- description: I2STX0 BCLK
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- description: external HDMI pixel
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clock-names:
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items:
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- const: vout_src
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- const: vout_top_ahb
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- const: vout_top_axi
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- const: vout_top_hdmitx0_mclk
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- const: i2stx0_bclk
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- const: hdmitx0_pixelclk
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resets:
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maxItems: 1
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description: Vout Top core
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'#clock-cells':
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const: 1
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description:
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See <dt-bindings/clock/starfive,jh7110-crg.h> for valid indices.
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'#reset-cells':
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const: 1
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description:
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See <dt-bindings/reset/starfive,jh7110-crg.h> for valid indices.
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power-domains:
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maxItems: 1
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description:
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Vout domain power
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- resets
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- '#clock-cells'
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- '#reset-cells'
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- power-domains
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/starfive,jh7110-crg.h>
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#include <dt-bindings/power/starfive,jh7110-pmu.h>
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#include <dt-bindings/reset/starfive,jh7110-crg.h>
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voutcrg: clock-controller@295C0000 {
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compatible = "starfive,jh7110-voutcrg";
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reg = <0x295C0000 0x10000>;
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clocks = <&syscrg JH7110_SYSCLK_VOUT_SRC>,
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<&syscrg JH7110_SYSCLK_VOUT_TOP_AHB>,
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<&syscrg JH7110_SYSCLK_VOUT_TOP_AXI>,
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<&syscrg JH7110_SYSCLK_VOUT_TOP_HDMITX0_MCLK>,
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<&syscrg JH7110_SYSCLK_I2STX0_BCLK>,
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<&hdmitx0_pixelclk>;
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clock-names = "vout_src", "vout_top_ahb",
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"vout_top_axi", "vout_top_hdmitx0_mclk",
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"i2stx0_bclk", "hdmitx0_pixelclk";
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resets = <&syscrg JH7110_SYSRST_VOUT_TOP_SRC>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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power-domains = <&pwrc JH7110_PD_VOUT>;
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};

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