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Mani-Sadhasivammiquelraynal
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mtd: rawnand: qcom: Unmap sg_list and free desc within submic_descs()
There are two types of dma descriptors being used in this driver allocated by, prepare_bam_async_desc() and prep_adm_dma_desc() helper functions. These functions map and prepare the descriptors to be used for dma transfers. And all the descriptors are submitted inside the submit_descs() function. Once the transfer completion happens, those descriptors should be unmapped and freed as a part of cleanup. Currently, free_descs() function is doing the said cleanup of descriptors. But the callers of submit_descs() are required to call free_descs() in both the success and error cases. Since there are no other transactions need to be done after submit_descs(), let's just move the contents of free_descs() inside submit_descs() itself. This makes sure that the cleanup is handled within the submit_descs() thereby offloading the cleanup part from callers. While at it, let's also rename the return variable from "r" to "ret". Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20230805174146.57006-8-manivannan.sadhasivam@linaro.org
1 parent cf82436 commit bb7a103

1 file changed

Lines changed: 20 additions & 45 deletions

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drivers/mtd/nand/raw/qcom_nandc.c

Lines changed: 20 additions & 45 deletions
Original file line numberDiff line numberDiff line change
@@ -1306,30 +1306,30 @@ static void config_nand_cw_write(struct nand_chip *chip)
13061306
/* helpers to submit/free our list of dma descriptors */
13071307
static int submit_descs(struct qcom_nand_controller *nandc)
13081308
{
1309-
struct desc_info *desc;
1309+
struct desc_info *desc, *n;
13101310
dma_cookie_t cookie = 0;
13111311
struct bam_transaction *bam_txn = nandc->bam_txn;
1312-
int r;
1312+
int ret = 0;
13131313

13141314
if (nandc->props->is_bam) {
13151315
if (bam_txn->rx_sgl_pos > bam_txn->rx_sgl_start) {
1316-
r = prepare_bam_async_desc(nandc, nandc->rx_chan, 0);
1317-
if (r)
1318-
return r;
1316+
ret = prepare_bam_async_desc(nandc, nandc->rx_chan, 0);
1317+
if (ret)
1318+
goto err_unmap_free_desc;
13191319
}
13201320

13211321
if (bam_txn->tx_sgl_pos > bam_txn->tx_sgl_start) {
1322-
r = prepare_bam_async_desc(nandc, nandc->tx_chan,
1322+
ret = prepare_bam_async_desc(nandc, nandc->tx_chan,
13231323
DMA_PREP_INTERRUPT);
1324-
if (r)
1325-
return r;
1324+
if (ret)
1325+
goto err_unmap_free_desc;
13261326
}
13271327

13281328
if (bam_txn->cmd_sgl_pos > bam_txn->cmd_sgl_start) {
1329-
r = prepare_bam_async_desc(nandc, nandc->cmd_chan,
1329+
ret = prepare_bam_async_desc(nandc, nandc->cmd_chan,
13301330
DMA_PREP_CMD);
1331-
if (r)
1332-
return r;
1331+
if (ret)
1332+
goto err_unmap_free_desc;
13331333
}
13341334
}
13351335

@@ -1351,19 +1351,17 @@ static int submit_descs(struct qcom_nand_controller *nandc)
13511351

13521352
if (!wait_for_completion_timeout(&bam_txn->txn_done,
13531353
QPIC_NAND_COMPLETION_TIMEOUT))
1354-
return -ETIMEDOUT;
1354+
ret = -ETIMEDOUT;
13551355
} else {
13561356
if (dma_sync_wait(nandc->chan, cookie) != DMA_COMPLETE)
1357-
return -ETIMEDOUT;
1357+
ret = -ETIMEDOUT;
13581358
}
13591359

1360-
return 0;
1361-
}
1362-
1363-
static void free_descs(struct qcom_nand_controller *nandc)
1364-
{
1365-
struct desc_info *desc, *n;
1366-
1360+
err_unmap_free_desc:
1361+
/*
1362+
* Unmap the dma sg_list and free the desc allocated by both
1363+
* prepare_bam_async_desc() and prep_adm_dma_desc() functions.
1364+
*/
13671365
list_for_each_entry_safe(desc, n, &nandc->desc_list, node) {
13681366
list_del(&desc->node);
13691367

@@ -1376,6 +1374,8 @@ static void free_descs(struct qcom_nand_controller *nandc)
13761374

13771375
kfree(desc);
13781376
}
1377+
1378+
return ret;
13791379
}
13801380

13811381
/* reset the register read buffer for next NAND operation */
@@ -1521,7 +1521,6 @@ qcom_nandc_read_cw_raw(struct mtd_info *mtd, struct nand_chip *chip,
15211521
read_data_dma(nandc, reg_off, oob_buf + oob_size1, oob_size2, 0);
15221522

15231523
ret = submit_descs(nandc);
1524-
free_descs(nandc);
15251524
if (ret) {
15261525
dev_err(nandc->dev, "failure to read raw cw %d\n", cw);
15271526
return ret;
@@ -1775,8 +1774,6 @@ static int read_page_ecc(struct qcom_nand_host *host, u8 *data_buf,
17751774
}
17761775

17771776
ret = submit_descs(nandc);
1778-
free_descs(nandc);
1779-
17801777
if (ret) {
17811778
dev_err(nandc->dev, "failure to read page/oob\n");
17821779
return ret;
@@ -1815,8 +1812,6 @@ static int copy_last_cw(struct qcom_nand_host *host, int page)
18151812
if (ret)
18161813
dev_err(nandc->dev, "failed to copy last codeword\n");
18171814

1818-
free_descs(nandc);
1819-
18201815
return ret;
18211816
}
18221817

@@ -2024,8 +2019,6 @@ static int qcom_nandc_write_page(struct nand_chip *chip, const u8 *buf,
20242019
if (ret)
20252020
dev_err(nandc->dev, "failure to write page\n");
20262021

2027-
free_descs(nandc);
2028-
20292022
if (!ret)
20302023
ret = nand_prog_page_end_op(chip);
20312024

@@ -2100,8 +2093,6 @@ static int qcom_nandc_write_page_raw(struct nand_chip *chip,
21002093
if (ret)
21012094
dev_err(nandc->dev, "failure to write raw page\n");
21022095

2103-
free_descs(nandc);
2104-
21052096
if (!ret)
21062097
ret = nand_prog_page_end_op(chip);
21072098

@@ -2149,9 +2140,6 @@ static int qcom_nandc_write_oob(struct nand_chip *chip, int page)
21492140
config_nand_cw_write(chip);
21502141

21512142
ret = submit_descs(nandc);
2152-
2153-
free_descs(nandc);
2154-
21552143
if (ret) {
21562144
dev_err(nandc->dev, "failure to write oob\n");
21572145
return -EIO;
@@ -2228,9 +2216,6 @@ static int qcom_nandc_block_markbad(struct nand_chip *chip, loff_t ofs)
22282216
config_nand_cw_write(chip);
22292217

22302218
ret = submit_descs(nandc);
2231-
2232-
free_descs(nandc);
2233-
22342219
if (ret) {
22352220
dev_err(nandc->dev, "failure to update BBM\n");
22362221
return -EIO;
@@ -2722,10 +2707,8 @@ static int qcom_read_status_exec(struct nand_chip *chip,
27222707
ret = submit_descs(nandc);
27232708
if (ret) {
27242709
dev_err(nandc->dev, "failure in submitting status descriptor\n");
2725-
free_descs(nandc);
27262710
goto err_out;
27272711
}
2728-
free_descs(nandc);
27292712

27302713
nandc_read_buffer_sync(nandc, true);
27312714

@@ -2787,10 +2770,8 @@ static int qcom_read_id_type_exec(struct nand_chip *chip, const struct nand_subo
27872770
ret = submit_descs(nandc);
27882771
if (ret) {
27892772
dev_err(nandc->dev, "failure in submitting read id descriptor\n");
2790-
free_descs(nandc);
27912773
goto err_out;
27922774
}
2793-
free_descs(nandc);
27942775

27952776
instr = q_op.data_instr;
27962777
op_id = q_op.data_instr_idx;
@@ -2835,10 +2816,8 @@ static int qcom_misc_cmd_type_exec(struct nand_chip *chip, const struct nand_sub
28352816
ret = submit_descs(nandc);
28362817
if (ret) {
28372818
dev_err(nandc->dev, "failure in submitting misc descriptor\n");
2838-
free_descs(nandc);
28392819
goto err_out;
28402820
}
2841-
free_descs(nandc);
28422821

28432822
wait_rdy:
28442823
qcom_delay_ns(q_op.rdy_delay_ns);
@@ -2932,10 +2911,8 @@ static int qcom_param_page_type_exec(struct nand_chip *chip, const struct nand_
29322911
ret = submit_descs(nandc);
29332912
if (ret) {
29342913
dev_err(nandc->dev, "failure in submitting param page descriptor\n");
2935-
free_descs(nandc);
29362914
goto err_out;
29372915
}
2938-
free_descs(nandc);
29392916

29402917
ret = qcom_wait_rdy_poll(chip, q_op.rdy_timeout_ms);
29412918
if (ret)
@@ -2981,10 +2958,8 @@ static int qcom_erase_cmd_type_exec(struct nand_chip *chip, const struct nand_su
29812958
ret = submit_descs(nandc);
29822959
if (ret) {
29832960
dev_err(nandc->dev, "failure in submitting erase descriptor\n");
2984-
free_descs(nandc);
29852961
goto err_out;
29862962
}
2987-
free_descs(nandc);
29882963

29892964
ret = qcom_wait_rdy_poll(chip, q_op.rdy_timeout_ms);
29902965
if (ret)

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