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Chunyan Zhang
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arm64: dts: sprd: Add support for Unisoc's UMS9620
Add basic support for Unisoc's UMS9620, with this patch, the board ums9620-2h10 can run into console. Link: https://lore.kernel.org/r/20231218100234.1102916-4-chunyan.zhang@unisoc.com Signed-off-by: Chunyan Zhang <chunyan.zhang@unisoc.com>
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‎arch/arm64/boot/dts/sprd/Makefile‎

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dtb-$(CONFIG_ARCH_SPRD) += sc9836-openphone.dtb \
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sp9860g-1h10.dtb \
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sp9863a-1h10.dtb \
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ums512-1h10.dtb
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ums512-1h10.dtb \
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ums9620-2h10.dtb

‎arch/arm64/boot/dts/sprd/ums9620-2h10.dts‎

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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/*
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* Unisoc UMS9620-2h10 board DTS file
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*
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* Copyright (C) 2023, Unisoc Inc.
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*/
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/dts-v1/;
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#include "ums9620.dtsi"
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/ {
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model = "Unisoc UMS9620-2H10 Board";
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compatible = "sprd,ums9620-2h10", "sprd,ums9620";
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aliases {
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serial0 = &uart0;
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serial1 = &uart1;
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};
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memory@80000000 {
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device_type = "memory";
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reg = <0x0 0x80000000 0x2 0x00000000>;
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};
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chosen {
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stdout-path = "serial1:921600n8";
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};
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};
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&uart0 {
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status = "okay";
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};
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&uart1 {
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status = "okay";
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};

‎arch/arm64/boot/dts/sprd/ums9620.dtsi‎

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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/*
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* Unisoc UMS9620 DTS file
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*
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* Copyright (C) 2023, Unisoc Inc.
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&CPU0>;
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};
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core1 {
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cpu = <&CPU1>;
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};
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core2 {
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cpu = <&CPU2>;
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};
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core3 {
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cpu = <&CPU3>;
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};
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core4 {
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cpu = <&CPU4>;
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};
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core5 {
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cpu = <&CPU5>;
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};
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core6 {
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cpu = <&CPU6>;
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};
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core7 {
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cpu = <&CPU7>;
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};
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};
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};
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CPU0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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reg = <0x0 0x0>;
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enable-method = "psci";
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cpu-idle-states = <&LIT_CORE_PD>;
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};
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CPU1: cpu@100 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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reg = <0x0 0x100>;
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enable-method = "psci";
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cpu-idle-states = <&LIT_CORE_PD>;
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};
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CPU2: cpu@200 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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reg = <0x0 0x200>;
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enable-method = "psci";
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cpu-idle-states = <&LIT_CORE_PD>;
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};
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CPU3: cpu@300 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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reg = <0x0 0x300>;
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enable-method = "psci";
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cpu-idle-states = <&LIT_CORE_PD>;
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};
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CPU4: cpu@400 {
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device_type = "cpu";
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compatible = "arm,cortex-a76";
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reg = <0x0 0x400>;
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enable-method = "psci";
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cpu-idle-states = <&BIG_CORE_PD>;
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};
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CPU5: cpu@500 {
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device_type = "cpu";
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compatible = "arm,cortex-a76";
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reg = <0x0 0x500>;
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enable-method = "psci";
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cpu-idle-states = <&BIG_CORE_PD>;
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};
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CPU6: cpu@600 {
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device_type = "cpu";
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compatible = "arm,cortex-a76";
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reg = <0x0 0x600>;
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enable-method = "psci";
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cpu-idle-states = <&BIG_CORE_PD>;
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};
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CPU7: cpu@700 {
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device_type = "cpu";
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compatible = "arm,cortex-a76";
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reg = <0x0 0x700>;
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enable-method = "psci";
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cpu-idle-states = <&BIG_CORE_PD>;
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};
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};
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idle-states {
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entry-method = "psci";
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LIT_CORE_PD: cpu-pd-lit {
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compatible = "arm,idle-state";
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entry-latency-us = <1000>;
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exit-latency-us = <500>;
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min-residency-us = <2500>;
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local-timer-stop;
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arm,psci-suspend-param = <0x00010000>;
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};
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BIG_CORE_PD: cpu-pd-big {
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compatible = "arm,idle-state";
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entry-latency-us = <4000>;
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exit-latency-us = <4000>;
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min-residency-us = <10000>;
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local-timer-stop;
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arm,psci-suspend-param = <0x00010000>;
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};
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};
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psci {
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compatible = "arm,psci-0.2";
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method = "smc";
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>, /* Physical Secure PPI */
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<GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>, /* Physical Non-Secure PPI */
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<GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>, /* Virtual PPI */
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<GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>; /* Hipervisor PPI */
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};
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pmu {
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compatible = "arm,armv8-pmuv3";
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interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
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};
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soc: soc {
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compatible = "simple-bus";
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ranges;
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#address-cells = <2>;
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#size-cells = <2>;
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gic: interrupt-controller@12000000 {
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compatible = "arm,gic-v3";
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reg = <0x0 0x12000000 0 0x20000>, /* GICD */
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<0x0 0x12040000 0 0x100000>; /* GICR */
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#interrupt-cells = <3>;
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#address-cells = <2>;
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#size-cells = <2>;
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redistributor-stride = <0x0 0x20000>; /* 128KB stride */
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#redistributor-regions = <1>;
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interrupt-controller;
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
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};
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apb@20200000 {
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compatible = "simple-bus";
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ranges = <0 0 0x20200000 0x100000>;
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#address-cells = <1>;
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#size-cells = <1>;
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uart0: serial@0 {
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compatible = "sprd,ums9620-uart",
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"sprd,sc9836-uart";
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reg = <0 0x100>;
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interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ext_26m>;
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status = "disabled";
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};
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uart1: serial@10000 {
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compatible = "sprd,ums9620-uart",
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"sprd,sc9836-uart";
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reg = <0x10000 0x100>;
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interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ext_26m>;
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status = "disabled";
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};
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};
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};
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ext_26m: clk-26m {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <26000000>;
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clock-output-names = "ext-26m";
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};
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ext_4m: clk-4m {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <4000000>;
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clock-output-names = "ext-4m";
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};
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ext_32k: clk-32k {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <32768>;
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clock-output-names = "ext-32k";
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};
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rco_100m: clk-100m {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <100000000>;
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clock-output-names = "rco-100m";
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};
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dphy_312m5: dphy-312m5 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <312500000>;
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clock-output-names = "dphy-312m5";
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};
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dphy_416m7: dphy-416m7 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <416700000>;
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clock-output-names = "dphy-416m7";
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};
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};

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