Skip to content

Commit bbb9686

Browse files
Kan LiangPeter Zijlstra
authored andcommitted
perf/x86/intel/cstate: Add Grand Ridge support
The same as the Sierra Forest, the Grand Ridge supports core C1/C6 and module C6. But it doesn't support pkg C6 residency counter. Signed-off-by: Kan Liang <kan.liang@linux.intel.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Link: https://lore.kernel.org/r/20231116142245.1233485-4-kan.liang@linux.intel.com
1 parent 3877d55 commit bbb9686

1 file changed

Lines changed: 12 additions & 3 deletions

File tree

arch/x86/events/intel/cstate.c

Lines changed: 12 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -41,7 +41,7 @@
4141
* MSR_CORE_C1_RES: CORE C1 Residency Counter
4242
* perf code: 0x00
4343
* Available model: SLM,AMT,GLM,CNL,ICX,TNT,ADL,RPL
44-
* MTL,SRF
44+
* MTL,SRF,GRR
4545
* Scope: Core (each processor core has a MSR)
4646
* MSR_CORE_C3_RESIDENCY: CORE C3 Residency Counter
4747
* perf code: 0x01
@@ -52,7 +52,8 @@
5252
* perf code: 0x02
5353
* Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW,
5454
* SKL,KNL,GLM,CNL,KBL,CML,ICL,ICX,
55-
* TGL,TNT,RKL,ADL,RPL,SPR,MTL,SRF
55+
* TGL,TNT,RKL,ADL,RPL,SPR,MTL,SRF,
56+
* GRR
5657
* Scope: Core
5758
* MSR_CORE_C7_RESIDENCY: CORE C7 Residency Counter
5859
* perf code: 0x03
@@ -99,7 +100,7 @@
99100
* Scope: Package (physical package)
100101
* MSR_MODULE_C6_RES_MS: Module C6 Residency Counter.
101102
* perf code: 0x00
102-
* Available model: SRF
103+
* Available model: SRF,GRR
103104
* Scope: A cluster of cores shared L2 cache
104105
*
105106
*/
@@ -677,6 +678,13 @@ static const struct cstate_model glm_cstates __initconst = {
677678
BIT(PERF_CSTATE_PKG_C10_RES),
678679
};
679680

681+
static const struct cstate_model grr_cstates __initconst = {
682+
.core_events = BIT(PERF_CSTATE_CORE_C1_RES) |
683+
BIT(PERF_CSTATE_CORE_C6_RES),
684+
685+
.module_events = BIT(PERF_CSTATE_MODULE_C6_RES),
686+
};
687+
680688
static const struct cstate_model srf_cstates __initconst = {
681689
.core_events = BIT(PERF_CSTATE_CORE_C1_RES) |
682690
BIT(PERF_CSTATE_CORE_C6_RES),
@@ -739,6 +747,7 @@ static const struct x86_cpu_id intel_cstates_match[] __initconst = {
739747
X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT_L, &glm_cstates),
740748
X86_MATCH_INTEL_FAM6_MODEL(ATOM_GRACEMONT, &adl_cstates),
741749
X86_MATCH_INTEL_FAM6_MODEL(ATOM_CRESTMONT_X, &srf_cstates),
750+
X86_MATCH_INTEL_FAM6_MODEL(ATOM_CRESTMONT, &grr_cstates),
742751

743752
X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_L, &icl_cstates),
744753
X86_MATCH_INTEL_FAM6_MODEL(ICELAKE, &icl_cstates),

0 commit comments

Comments
 (0)