Skip to content

Commit bc27020

Browse files
tretterbebarino
tretter
authored and
bebarino
committed
soc: xilinx: vcu: use bitfields for register definition
This makes the register accesses more readable and is closer to what is usually used in the kernel. Signed-off-by: Michael Tretter <m.tretter@pengutronix.de> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Acked-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/20210121071659.1226489-13-m.tretter@pengutronix.de Signed-off-by: Stephen Boyd <sboyd@kernel.org>
1 parent 5a9b125 commit bc27020

1 file changed

Lines changed: 34 additions & 81 deletions

File tree

‎drivers/soc/xilinx/xlnx_vcu.c‎

Lines changed: 34 additions & 81 deletions
Original file line numberDiff line numberDiff line change
@@ -6,6 +6,7 @@
66
*
77
* Contacts Dhaval Shah <dshah@xilinx.com>
88
*/
9+
#include <linux/bitfield.h>
910
#include <linux/clk.h>
1011
#include <linux/clk-provider.h>
1112
#include <linux/device.h>
@@ -20,41 +21,26 @@
2021

2122
#include <dt-bindings/clock/xlnx-vcu.h>
2223

23-
/* vcu slcr registers, bitmask and shift */
2424
#define VCU_PLL_CTRL 0x24
25-
#define VCU_PLL_CTRL_RESET_MASK 0x01
26-
#define VCU_PLL_CTRL_RESET_SHIFT 0
27-
#define VCU_PLL_CTRL_BYPASS_MASK 0x01
28-
#define VCU_PLL_CTRL_BYPASS_SHIFT 3
29-
#define VCU_PLL_CTRL_FBDIV_MASK 0x7f
30-
#define VCU_PLL_CTRL_FBDIV_SHIFT 8
31-
#define VCU_PLL_CTRL_POR_IN_MASK 0x01
32-
#define VCU_PLL_CTRL_POR_IN_SHIFT 1
33-
#define VCU_PLL_CTRL_PWR_POR_MASK 0x01
34-
#define VCU_PLL_CTRL_PWR_POR_SHIFT 2
35-
#define VCU_PLL_CTRL_CLKOUTDIV_MASK 0x03
36-
#define VCU_PLL_CTRL_CLKOUTDIV_SHIFT 16
37-
#define VCU_PLL_CTRL_DEFAULT 0
38-
#define VCU_PLL_DIV2 2
25+
#define VCU_PLL_CTRL_RESET BIT(0)
26+
#define VCU_PLL_CTRL_POR_IN BIT(1)
27+
#define VCU_PLL_CTRL_PWR_POR BIT(2)
28+
#define VCU_PLL_CTRL_BYPASS BIT(3)
29+
#define VCU_PLL_CTRL_FBDIV GENMASK(14, 8)
30+
#define VCU_PLL_CTRL_CLKOUTDIV GENMASK(18, 16)
3931

4032
#define VCU_PLL_CFG 0x28
41-
#define VCU_PLL_CFG_RES_MASK 0x0f
42-
#define VCU_PLL_CFG_RES_SHIFT 0
43-
#define VCU_PLL_CFG_CP_MASK 0x0f
44-
#define VCU_PLL_CFG_CP_SHIFT 5
45-
#define VCU_PLL_CFG_LFHF_MASK 0x03
46-
#define VCU_PLL_CFG_LFHF_SHIFT 10
47-
#define VCU_PLL_CFG_LOCK_CNT_MASK 0x03ff
48-
#define VCU_PLL_CFG_LOCK_CNT_SHIFT 13
49-
#define VCU_PLL_CFG_LOCK_DLY_MASK 0x7f
50-
#define VCU_PLL_CFG_LOCK_DLY_SHIFT 25
33+
#define VCU_PLL_CFG_RES GENMASK(3, 0)
34+
#define VCU_PLL_CFG_CP GENMASK(8, 5)
35+
#define VCU_PLL_CFG_LFHF GENMASK(12, 10)
36+
#define VCU_PLL_CFG_LOCK_CNT GENMASK(22, 13)
37+
#define VCU_PLL_CFG_LOCK_DLY GENMASK(31, 25)
5138
#define VCU_ENC_CORE_CTRL 0x30
5239
#define VCU_ENC_MCU_CTRL 0x34
5340
#define VCU_DEC_CORE_CTRL 0x38
5441
#define VCU_DEC_MCU_CTRL 0x3c
55-
5642
#define VCU_PLL_STATUS 0x60
57-
#define VCU_PLL_STATUS_LOCK_STATUS_MASK 0x01
43+
#define VCU_PLL_STATUS_LOCK_STATUS BIT(0)
5844

5945
#define MHZ 1000000
6046
#define FVCO_MIN (1500U * MHZ)
@@ -237,25 +223,6 @@ static inline void xvcu_write(void __iomem *iomem, u32 offset, u32 value)
237223
iowrite32(value, iomem + offset);
238224
}
239225

240-
/**
241-
* xvcu_write_field_reg - Write to the vcu reg field
242-
* @iomem: vcu reg space base address
243-
* @offset: vcu reg offset from base
244-
* @field: vcu reg field to write to
245-
* @mask: vcu reg mask
246-
* @shift: vcu reg number of bits to shift the bitfield
247-
*/
248-
static void xvcu_write_field_reg(void __iomem *iomem, int offset,
249-
u32 field, u32 mask, int shift)
250-
{
251-
u32 val = xvcu_read(iomem, offset);
252-
253-
val &= ~(mask << shift);
254-
val |= (field & mask) << shift;
255-
256-
xvcu_write(iomem, offset, val);
257-
}
258-
259226
#define to_vcu_pll(_hw) container_of(_hw, struct vcu_pll, hw)
260227

261228
struct vcu_pll {
@@ -274,7 +241,7 @@ static int xvcu_pll_wait_for_lock(struct vcu_pll *pll)
274241
timeout = jiffies + msecs_to_jiffies(2000);
275242
do {
276243
lock_status = xvcu_read(base, VCU_PLL_STATUS);
277-
if (lock_status & VCU_PLL_STATUS_LOCK_STATUS_MASK)
244+
if (lock_status & VCU_PLL_STATUS_LOCK_STATUS)
278245
return 0;
279246
} while (!time_after(jiffies, timeout));
280247

@@ -294,8 +261,7 @@ static struct clk_hw *xvcu_register_pll_post(struct device *dev,
294261
* timing in the design.
295262
*/
296263
vcu_pll_ctrl = xvcu_read(reg_base, VCU_PLL_CTRL);
297-
div = vcu_pll_ctrl >> VCU_PLL_CTRL_CLKOUTDIV_SHIFT;
298-
div = div & VCU_PLL_CTRL_CLKOUTDIV_MASK;
264+
div = FIELD_GET(VCU_PLL_CTRL_CLKOUTDIV, vcu_pll_ctrl);
299265
if (div != 1)
300266
return ERR_PTR(-EINVAL);
301267

@@ -328,16 +294,15 @@ static int xvcu_pll_set_div(struct vcu_pll *pll, int div)
328294
return -EINVAL;
329295

330296
vcu_pll_ctrl = xvcu_read(base, VCU_PLL_CTRL);
331-
vcu_pll_ctrl &= ~(VCU_PLL_CTRL_FBDIV_MASK << VCU_PLL_CTRL_FBDIV_SHIFT);
332-
vcu_pll_ctrl |= (cfg->fbdiv & VCU_PLL_CTRL_FBDIV_MASK) <<
333-
VCU_PLL_CTRL_FBDIV_SHIFT;
297+
vcu_pll_ctrl &= ~VCU_PLL_CTRL_FBDIV;
298+
vcu_pll_ctrl |= FIELD_PREP(VCU_PLL_CTRL_FBDIV, cfg->fbdiv);
334299
xvcu_write(base, VCU_PLL_CTRL, vcu_pll_ctrl);
335300

336-
cfg_val = (cfg->res << VCU_PLL_CFG_RES_SHIFT) |
337-
(cfg->cp << VCU_PLL_CFG_CP_SHIFT) |
338-
(cfg->lfhf << VCU_PLL_CFG_LFHF_SHIFT) |
339-
(cfg->lock_cnt << VCU_PLL_CFG_LOCK_CNT_SHIFT) |
340-
(cfg->lock_dly << VCU_PLL_CFG_LOCK_DLY_SHIFT);
301+
cfg_val = FIELD_PREP(VCU_PLL_CFG_RES, cfg->res) |
302+
FIELD_PREP(VCU_PLL_CFG_CP, cfg->cp) |
303+
FIELD_PREP(VCU_PLL_CFG_LFHF, cfg->lfhf) |
304+
FIELD_PREP(VCU_PLL_CFG_LOCK_CNT, cfg->lock_cnt) |
305+
FIELD_PREP(VCU_PLL_CFG_LOCK_DLY, cfg->lock_dly);
341306
xvcu_write(base, VCU_PLL_CFG, cfg_val);
342307

343308
return 0;
@@ -366,7 +331,7 @@ static unsigned long xvcu_pll_recalc_rate(struct clk_hw *hw,
366331
u32 vcu_pll_ctrl;
367332

368333
vcu_pll_ctrl = xvcu_read(base, VCU_PLL_CTRL);
369-
div = (vcu_pll_ctrl >> VCU_PLL_CTRL_FBDIV_SHIFT) & VCU_PLL_CTRL_FBDIV_MASK;
334+
div = FIELD_GET(VCU_PLL_CTRL_FBDIV, vcu_pll_ctrl);
370335

371336
return div * parent_rate;
372337
}
@@ -386,23 +351,14 @@ static int xvcu_pll_enable(struct clk_hw *hw)
386351
u32 vcu_pll_ctrl;
387352
int ret;
388353

389-
xvcu_write_field_reg(base, VCU_PLL_CTRL,
390-
1, VCU_PLL_CTRL_BYPASS_MASK,
391-
VCU_PLL_CTRL_BYPASS_SHIFT);
392-
393354
vcu_pll_ctrl = xvcu_read(base, VCU_PLL_CTRL);
394-
vcu_pll_ctrl &= ~(VCU_PLL_CTRL_POR_IN_MASK <<
395-
VCU_PLL_CTRL_POR_IN_SHIFT);
396-
vcu_pll_ctrl |= (VCU_PLL_CTRL_DEFAULT & VCU_PLL_CTRL_POR_IN_MASK) <<
397-
VCU_PLL_CTRL_POR_IN_SHIFT;
398-
vcu_pll_ctrl &= ~(VCU_PLL_CTRL_PWR_POR_MASK <<
399-
VCU_PLL_CTRL_PWR_POR_SHIFT);
400-
vcu_pll_ctrl |= (VCU_PLL_CTRL_DEFAULT & VCU_PLL_CTRL_PWR_POR_MASK) <<
401-
VCU_PLL_CTRL_PWR_POR_SHIFT;
355+
vcu_pll_ctrl |= VCU_PLL_CTRL_BYPASS;
402356
xvcu_write(base, VCU_PLL_CTRL, vcu_pll_ctrl);
403357

404-
vcu_pll_ctrl &= ~(VCU_PLL_CTRL_RESET_MASK << VCU_PLL_CTRL_RESET_SHIFT);
405-
vcu_pll_ctrl |= (0 & VCU_PLL_CTRL_RESET_MASK) << VCU_PLL_CTRL_RESET_SHIFT;
358+
vcu_pll_ctrl = xvcu_read(base, VCU_PLL_CTRL);
359+
vcu_pll_ctrl &= ~VCU_PLL_CTRL_POR_IN;
360+
vcu_pll_ctrl &= ~VCU_PLL_CTRL_PWR_POR;
361+
vcu_pll_ctrl &= ~VCU_PLL_CTRL_RESET;
406362
xvcu_write(base, VCU_PLL_CTRL, vcu_pll_ctrl);
407363

408364
ret = xvcu_pll_wait_for_lock(pll);
@@ -411,9 +367,9 @@ static int xvcu_pll_enable(struct clk_hw *hw)
411367
goto err;
412368
}
413369

414-
xvcu_write_field_reg(base, VCU_PLL_CTRL,
415-
0, VCU_PLL_CTRL_BYPASS_MASK,
416-
VCU_PLL_CTRL_BYPASS_SHIFT);
370+
vcu_pll_ctrl = xvcu_read(base, VCU_PLL_CTRL);
371+
vcu_pll_ctrl &= ~VCU_PLL_CTRL_BYPASS;
372+
xvcu_write(base, VCU_PLL_CTRL, vcu_pll_ctrl);
417373

418374
err:
419375
return ret;
@@ -426,12 +382,9 @@ static void xvcu_pll_disable(struct clk_hw *hw)
426382
u32 vcu_pll_ctrl;
427383

428384
vcu_pll_ctrl = xvcu_read(base, VCU_PLL_CTRL);
429-
vcu_pll_ctrl &= ~(VCU_PLL_CTRL_POR_IN_MASK << VCU_PLL_CTRL_POR_IN_SHIFT);
430-
vcu_pll_ctrl |= (1 & VCU_PLL_CTRL_POR_IN_MASK) << VCU_PLL_CTRL_POR_IN_SHIFT;
431-
vcu_pll_ctrl &= ~(VCU_PLL_CTRL_PWR_POR_MASK << VCU_PLL_CTRL_PWR_POR_SHIFT);
432-
vcu_pll_ctrl |= (1 & VCU_PLL_CTRL_PWR_POR_MASK) << VCU_PLL_CTRL_PWR_POR_SHIFT;
433-
vcu_pll_ctrl &= ~(VCU_PLL_CTRL_RESET_MASK << VCU_PLL_CTRL_RESET_SHIFT);
434-
vcu_pll_ctrl |= (1 & VCU_PLL_CTRL_RESET_MASK) << VCU_PLL_CTRL_RESET_SHIFT;
385+
vcu_pll_ctrl |= VCU_PLL_CTRL_POR_IN;
386+
vcu_pll_ctrl |= VCU_PLL_CTRL_PWR_POR;
387+
vcu_pll_ctrl |= VCU_PLL_CTRL_RESET;
435388
xvcu_write(base, VCU_PLL_CTRL, vcu_pll_ctrl);
436389
}
437390

0 commit comments

Comments
 (0)