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AngeloGioacchino Del Regnombgg
AngeloGioacchino Del Regno
authored and
mbgg
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arm64: dts: mediatek: mt6795: Add support for display blocks and DPI/DSI
Introduce all nodes for all of the display blocks in the MediaTek Helio X10 MT6795 SoC, including the DSI PHY and DSI/DPI interfaces: those are left disabled as usage is board specific. Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20230721082822.680010-2-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
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‎arch/arm64/boot/dts/mediatek/mt6795.dtsi‎

Lines changed: 252 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,9 @@
11
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2015 MediaTek Inc.
4-
* Author: Mars.C <mars.cheng@mediatek.com>
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* Copyright (C) 2023 Collabora Ltd.
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* Authors: Mars.C <mars.cheng@mediatek.com>
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* AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
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*/
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#include <dt-bindings/interrupt-controller/irq.h>
@@ -19,6 +21,23 @@
1921
#address-cells = <2>;
2022
#size-cells = <2>;
2123

24+
aliases {
25+
ovl0 = &ovl0;
26+
ovl1 = &ovl1;
27+
rdma0 = &rdma0;
28+
rdma1 = &rdma1;
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rdma2 = &rdma2;
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wdma0 = &wdma0;
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wdma1 = &wdma1;
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color0 = &color0;
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color1 = &color1;
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split0 = &split0;
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split1 = &split1;
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dpi0 = &dpi0;
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dsi0 = &dsi0;
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dsi1 = &dsi1;
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};
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2241
psci {
2342
compatible = "arm,psci-0.2";
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method = "smc";
@@ -434,6 +453,26 @@
434453
#mbox-cells = <2>;
435454
};
436455

456+
mipi_tx0: dsi-phy@10215000 {
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compatible = "mediatek,mt8173-mipi-tx";
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reg = <0 0x10215000 0 0x1000>;
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clocks = <&clk26m>;
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clock-output-names = "mipi_tx0_pll";
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#clock-cells = <0>;
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#phy-cells = <0>;
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status = "disabled";
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};
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mipi_tx1: dsi-phy@10216000 {
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compatible = "mediatek,mt8173-mipi-tx";
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reg = <0 0x10216000 0 0x1000>;
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clocks = <&clk26m>;
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clock-output-names = "mipi_tx1_pll";
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#clock-cells = <0>;
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#phy-cells = <0>;
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status = "disabled";
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};
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437476
gic: interrupt-controller@10221000 {
438477
compatible = "arm,gic-400";
439478
#interrupt-cells = <3>;
@@ -690,6 +729,211 @@
690729
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
691730
};
692731

732+
ovl0: ovl@1400c000 {
733+
compatible = "mediatek,mt6795-disp-ovl", "mediatek,mt8173-disp-ovl";
734+
reg = <0 0x1400c000 0 0x1000>;
735+
interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_LOW>;
736+
power-domains = <&spm MT6795_POWER_DOMAIN_MM>;
737+
clocks = <&mmsys CLK_MM_DISP_OVL0>;
738+
iommus = <&iommu M4U_PORT_DISP_OVL0>;
739+
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
740+
};
741+
742+
ovl1: ovl@1400d000 {
743+
compatible = "mediatek,mt6795-disp-ovl", "mediatek,mt8173-disp-ovl";
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reg = <0 0x1400d000 0 0x1000>;
745+
interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_LOW>;
746+
power-domains = <&spm MT6795_POWER_DOMAIN_MM>;
747+
clocks = <&mmsys CLK_MM_DISP_OVL1>;
748+
iommus = <&iommu M4U_PORT_DISP_OVL1>;
749+
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>;
750+
};
751+
752+
rdma0: rdma@1400e000 {
753+
compatible = "mediatek,mt6795-disp-rdma", "mediatek,mt8173-disp-rdma";
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reg = <0 0x1400e000 0 0x1000>;
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interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_LOW>;
756+
power-domains = <&spm MT6795_POWER_DOMAIN_MM>;
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clocks = <&mmsys CLK_MM_DISP_RDMA0>;
758+
iommus = <&iommu M4U_PORT_DISP_RDMA0>;
759+
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
760+
};
761+
762+
rdma1: rdma@1400f000 {
763+
compatible = "mediatek,mt6795-disp-rdma", "mediatek,mt8173-disp-rdma";
764+
reg = <0 0x1400f000 0 0x1000>;
765+
interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_LOW>;
766+
power-domains = <&spm MT6795_POWER_DOMAIN_MM>;
767+
clocks = <&mmsys CLK_MM_DISP_RDMA1>;
768+
iommus = <&iommu M4U_PORT_DISP_RDMA1>;
769+
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>;
770+
};
771+
772+
rdma2: rdma@14010000 {
773+
compatible = "mediatek,mt6795-disp-rdma", "mediatek,mt8173-disp-rdma";
774+
reg = <0 0x14010000 0 0x1000>;
775+
interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_LOW>;
776+
power-domains = <&spm MT6795_POWER_DOMAIN_MM>;
777+
clocks = <&mmsys CLK_MM_DISP_RDMA2>;
778+
iommus = <&iommu M4U_PORT_DISP_RDMA2>;
779+
mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0 0x1000>;
780+
};
781+
782+
wdma0: wdma@14011000 {
783+
compatible = "mediatek,mt6795-disp-wdma", "mediatek,mt8173-disp-wdma";
784+
reg = <0 0x14011000 0 0x1000>;
785+
interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>;
786+
power-domains = <&spm MT6795_POWER_DOMAIN_MM>;
787+
clocks = <&mmsys CLK_MM_DISP_WDMA0>;
788+
iommus = <&iommu M4U_PORT_DISP_WDMA0>;
789+
mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>;
790+
};
791+
792+
wdma1: wdma@14012000 {
793+
compatible = "mediatek,mt6795-disp-wdma", "mediatek,mt8173-disp-wdma";
794+
reg = <0 0x14012000 0 0x1000>;
795+
interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>;
796+
power-domains = <&spm MT6795_POWER_DOMAIN_MM>;
797+
clocks = <&mmsys CLK_MM_DISP_WDMA1>;
798+
iommus = <&iommu M4U_PORT_DISP_WDMA1>;
799+
mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>;
800+
};
801+
802+
color0: color@14013000 {
803+
compatible = "mediatek,mt6795-disp-color", "mediatek,mt8173-disp-color";
804+
reg = <0 0x14013000 0 0x1000>;
805+
interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
806+
power-domains = <&spm MT6795_POWER_DOMAIN_MM>;
807+
clocks = <&mmsys CLK_MM_DISP_COLOR0>;
808+
mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x3000 0x1000>;
809+
};
810+
811+
color1: color@14014000 {
812+
compatible = "mediatek,mt6795-disp-color", "mediatek,mt8173-disp-color";
813+
reg = <0 0x14014000 0 0x1000>;
814+
interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_LOW>;
815+
power-domains = <&spm MT6795_POWER_DOMAIN_MM>;
816+
clocks = <&mmsys CLK_MM_DISP_COLOR1>;
817+
mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x4000 0x1000>;
818+
};
819+
820+
aal@14015000 {
821+
compatible = "mediatek,mt6795-disp-aal", "mediatek,mt8173-disp-aal";
822+
reg = <0 0x14015000 0 0x1000>;
823+
interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_LOW>;
824+
power-domains = <&spm MT6795_POWER_DOMAIN_MM>;
825+
clocks = <&mmsys CLK_MM_DISP_AAL>;
826+
mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>;
827+
};
828+
829+
gamma@14016000 {
830+
compatible = "mediatek,mt6795-disp-gamma", "mediatek,mt8173-disp-gamma";
831+
reg = <0 0x14016000 0 0x1000>;
832+
interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>;
833+
power-domains = <&spm MT6795_POWER_DOMAIN_MM>;
834+
clocks = <&mmsys CLK_MM_DISP_GAMMA>;
835+
mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x6000 0x1000>;
836+
};
837+
838+
merge@14017000 {
839+
compatible = "mediatek,mt6795-disp-merge", "mediatek,mt8173-disp-merge";
840+
reg = <0 0x14017000 0 0x1000>;
841+
power-domains = <&spm MT6795_POWER_DOMAIN_MM>;
842+
clocks = <&mmsys CLK_MM_DISP_MERGE>;
843+
};
844+
845+
split0: split@14018000 {
846+
compatible = "mediatek,mt6795-disp-split", "mediatek,mt8173-disp-split";
847+
reg = <0 0x14018000 0 0x1000>;
848+
power-domains = <&spm MT6795_POWER_DOMAIN_MM>;
849+
clocks = <&mmsys CLK_MM_DISP_SPLIT0>;
850+
};
851+
852+
split1: split@14019000 {
853+
compatible = "mediatek,mt6795-disp-split", "mediatek,mt8173-disp-split";
854+
reg = <0 0x14019000 0 0x1000>;
855+
power-domains = <&spm MT6795_POWER_DOMAIN_MM>;
856+
clocks = <&mmsys CLK_MM_DISP_SPLIT1>;
857+
};
858+
859+
ufoe@1401a000 {
860+
compatible = "mediatek,mt6795-disp-ufoe", "mediatek,mt8173-disp-ufoe";
861+
reg = <0 0x1401a000 0 0x1000>;
862+
interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_LOW>;
863+
power-domains = <&spm MT6795_POWER_DOMAIN_MM>;
864+
clocks = <&mmsys CLK_MM_DISP_UFOE>;
865+
mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0xa000 0x1000>;
866+
};
867+
868+
dsi0: dsi@1401b000 {
869+
compatible = "mediatek,mt6795-dsi", "mediatek,mt8173-dsi";
870+
reg = <0 0x1401b000 0 0x1000>;
871+
interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW>;
872+
power-domains = <&spm MT6795_POWER_DOMAIN_MM>;
873+
clocks = <&mmsys CLK_MM_DSI0_ENGINE>,
874+
<&mmsys CLK_MM_DSI0_DIGITAL>,
875+
<&mipi_tx0>;
876+
clock-names = "engine", "digital", "hs";
877+
phys = <&mipi_tx0>;
878+
phy-names = "dphy";
879+
status = "disabled";
880+
};
881+
882+
dsi1: dsi@1401c000 {
883+
compatible = "mediatek,mt6795-dsi", "mediatek,mt8173-dsi";
884+
reg = <0 0x1401c000 0 0x1000>;
885+
interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_LOW>;
886+
power-domains = <&spm MT6795_POWER_DOMAIN_MM>;
887+
clocks = <&mmsys CLK_MM_DSI1_ENGINE>,
888+
<&mmsys CLK_MM_DSI1_DIGITAL>,
889+
<&mipi_tx1>;
890+
clock-names = "engine", "digital", "hs";
891+
phys = <&mipi_tx1>;
892+
phy-names = "dphy";
893+
status = "disabled";
894+
};
895+
896+
dpi0: dpi@1401d000 {
897+
compatible = "mediatek,mt6795-dpi", "mediatek,mt8183-dpi";
898+
reg = <0 0x1401d000 0 0x1000>;
899+
interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_LOW>;
900+
power-domains = <&spm MT6795_POWER_DOMAIN_MM>;
901+
clocks = <&mmsys CLK_MM_DPI_PIXEL>,
902+
<&mmsys CLK_MM_DPI_ENGINE>,
903+
<&apmixedsys CLK_APMIXED_TVDPLL>;
904+
clock-names = "pixel", "engine", "pll";
905+
status = "disabled";
906+
};
907+
908+
pwm0: pwm@1401e000 {
909+
compatible = "mediatek,mt6795-disp-pwm", "mediatek,mt8173-disp-pwm";
910+
reg = <0 0x1401e000 0 0x1000>;
911+
#pwm-cells = <2>;
912+
clocks = <&mmsys CLK_MM_DISP_PWM026M>, <&mmsys CLK_MM_DISP_PWM0MM>;
913+
clock-names = "main", "mm";
914+
status = "disabled";
915+
};
916+
917+
pwm1: pwm@1401f000 {
918+
compatible = "mediatek,mt6795-disp-pwm", "mediatek,mt8173-disp-pwm";
919+
reg = <0 0x1401f000 0 0x1000>;
920+
#pwm-cells = <2>;
921+
clocks = <&mmsys CLK_MM_DISP_PWM126M>, <&mmsys CLK_MM_DISP_PWM1MM>;
922+
clock-names = "main", "mm";
923+
status = "disabled";
924+
};
925+
926+
mutex: mutex@14020000 {
927+
compatible = "mediatek,mt8173-disp-mutex";
928+
reg = <0 0x14020000 0 0x1000>;
929+
interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_LOW>;
930+
power-domains = <&spm MT6795_POWER_DOMAIN_MM>;
931+
clocks = <&mmsys CLK_MM_MUTEX_32K>;
932+
mediatek,gce-events = <CMDQ_EVENT_MUTEX0_STREAM_EOF>,
933+
<CMDQ_EVENT_MUTEX1_STREAM_EOF>;
934+
mediatek,gce-client-reg = <&gce SUBSYS_1402XXXX 0 0x1000>;
935+
};
936+
693937
larb0: larb@14021000 {
694938
compatible = "mediatek,mt6795-smi-larb";
695939
reg = <0 0x14021000 0 0x1000>;
@@ -708,6 +952,13 @@
708952
clock-names = "apb", "smi";
709953
};
710954

955+
od@14023000 {
956+
compatible = "mediatek,mt6795-disp-od", "mediatek,mt8173-disp-od";
957+
reg = <0 0x14023000 0 0x1000>;
958+
clocks = <&mmsys CLK_MM_DISP_OD>;
959+
mediatek,gce-client-reg = <&gce SUBSYS_1402XXXX 0x3000 0x1000>;
960+
};
961+
711962
larb2: larb@15001000 {
712963
compatible = "mediatek,mt6795-smi-larb";
713964
reg = <0 0x15001000 0 0x1000>;

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