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hvilleneuvedoogregkh
hvilleneuvedoo
authored and
gregkh
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serial: sc16is7xx: reformat comments to improve readability
Fold some multi-line comments into a single line, taking advantage of the new 100 line length limit to improve readability and to have uniform style across driver. Add missing 's' to SC16IS7XX_MCR_TCRTLR_BIT registers comments. Signed-off-by: Hugo Villeneuve <hvilleneuve@dimonoff.com> Link: https://patch.msgid.link/20251027142957.1032073-14-hugo@hugovil.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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Lines changed: 39 additions & 82 deletions

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‎drivers/tty/serial/sc16is7xx.c‎

Lines changed: 39 additions & 82 deletions
Original file line numberDiff line numberDiff line change
@@ -50,18 +50,10 @@
5050
#define SC16IS7XX_SPR_REG (0x07) /* Scratch Pad */
5151
#define SC16IS7XX_TXLVL_REG (0x08) /* TX FIFO level */
5252
#define SC16IS7XX_RXLVL_REG (0x09) /* RX FIFO level */
53-
#define SC16IS7XX_IODIR_REG (0x0a) /* I/O Direction
54-
* - only on 75x/76x
55-
*/
56-
#define SC16IS7XX_IOSTATE_REG (0x0b) /* I/O State
57-
* - only on 75x/76x
58-
*/
59-
#define SC16IS7XX_IOINTENA_REG (0x0c) /* I/O Interrupt Enable
60-
* - only on 75x/76x
61-
*/
62-
#define SC16IS7XX_IOCONTROL_REG (0x0e) /* I/O Control
63-
* - only on 75x/76x
64-
*/
53+
#define SC16IS7XX_IODIR_REG (0x0a) /* I/O Direction - only on 75x/76x */
54+
#define SC16IS7XX_IOSTATE_REG (0x0b) /* I/O State - only on 75x/76x */
55+
#define SC16IS7XX_IOINTENA_REG (0x0c) /* I/O Interrupt Enable - only on 75x/76x */
56+
#define SC16IS7XX_IOCONTROL_REG (0x0e) /* I/O Control - only on 75x/76x */
6557
#define SC16IS7XX_EFCR_REG (0x0f) /* Extra Features Control */
6658

6759
/* TCR/TLR Register set: Only if ((MCR[2] == 1) && (EFR[4] == 1)) */
@@ -81,12 +73,9 @@
8173

8274
/* IER register bits */
8375
#define SC16IS7XX_IER_RDI_BIT BIT(0) /* Enable RX data interrupt */
84-
#define SC16IS7XX_IER_THRI_BIT BIT(1) /* Enable TX holding register
85-
* interrupt */
86-
#define SC16IS7XX_IER_RLSI_BIT BIT(2) /* Enable RX line status
87-
* interrupt */
88-
#define SC16IS7XX_IER_MSI_BIT BIT(3) /* Enable Modem status
89-
* interrupt */
76+
#define SC16IS7XX_IER_THRI_BIT BIT(1) /* Enable TX holding register interrupt */
77+
#define SC16IS7XX_IER_RLSI_BIT BIT(2) /* Enable RX line status interrupt */
78+
#define SC16IS7XX_IER_MSI_BIT BIT(3) /* Enable Modem status interrupt */
9079

9180
/* IER register bits - write only if (EFR[4] == 1) */
9281
#define SC16IS7XX_IER_SLEEP_BIT BIT(4) /* Enable Sleep mode */
@@ -119,9 +108,8 @@
119108
* - only on 75x/76x
120109
*/
121110
#define SC16IS7XX_IIR_XOFFI_SRC 0x10 /* Received Xoff */
122-
#define SC16IS7XX_IIR_CTSRTS_SRC 0x20 /* nCTS,nRTS change of state
123-
* from active (LOW)
124-
* to inactive (HIGH)
111+
#define SC16IS7XX_IIR_CTSRTS_SRC 0x20 /* nCTS,nRTS change of state from active
112+
* (LOW) to inactive (HIGH)
125113
*/
126114
/* LCR register bits */
127115
#define SC16IS7XX_LCR_LENGTH0_BIT BIT(0) /* Word length bit 0 */
@@ -137,8 +125,7 @@
137125
*
138126
* STOP length bit table:
139127
* 0 -> 1 stop bit
140-
* 1 -> 1-1.5 stop bits if
141-
* word length is 5,
128+
* 1 -> 1-1.5 stop bits if word length is 5,
142129
* 2 stop bits otherwise
143130
*/
144131
#define SC16IS7XX_LCR_PARITY_BIT BIT(3) /* Parity bit enable */
@@ -150,31 +137,22 @@
150137
#define SC16IS7XX_LCR_WORD_LEN_6 (0x01)
151138
#define SC16IS7XX_LCR_WORD_LEN_7 (0x02)
152139
#define SC16IS7XX_LCR_WORD_LEN_8 (0x03)
153-
#define SC16IS7XX_LCR_REG_SET_SPECIAL SC16IS7XX_LCR_DLAB_BIT /* Special
154-
* reg set
155-
*/
156-
#define SC16IS7XX_LCR_REG_SET_ENHANCED 0xBF /* Enhanced
157-
* reg set
158-
*/
140+
#define SC16IS7XX_LCR_REG_SET_SPECIAL SC16IS7XX_LCR_DLAB_BIT /* Special reg set */
141+
#define SC16IS7XX_LCR_REG_SET_ENHANCED 0xBF /* Enhanced reg set */
159142

160143
/* MCR register bits */
161-
#define SC16IS7XX_MCR_DTR_BIT BIT(0) /* DTR complement
162-
* - only on 75x/76x
163-
*/
144+
#define SC16IS7XX_MCR_DTR_BIT BIT(0) /* DTR complement - only on 75x/76x */
164145
#define SC16IS7XX_MCR_RTS_BIT BIT(1) /* RTS complement */
165-
#define SC16IS7XX_MCR_TCRTLR_BIT BIT(2) /* TCR/TLR register enable */
146+
#define SC16IS7XX_MCR_TCRTLR_BIT BIT(2) /* TCR/TLR registers enable */
166147
#define SC16IS7XX_MCR_LOOP_BIT BIT(4) /* Enable loopback test mode */
167148
#define SC16IS7XX_MCR_XONANY_BIT BIT(5) /* Enable Xon Any
168-
* - write enabled
169-
* if (EFR[4] == 1)
149+
* - write enabled if (EFR[4] == 1)
170150
*/
171151
#define SC16IS7XX_MCR_IRDA_BIT BIT(6) /* Enable IrDA mode
172-
* - write enabled
173-
* if (EFR[4] == 1)
152+
* - write enabled if (EFR[4] == 1)
174153
*/
175154
#define SC16IS7XX_MCR_CLKSEL_BIT BIT(7) /* Divide clock by 4
176-
* - write enabled
177-
* if (EFR[4] == 1)
155+
* - write enabled if (EFR[4] == 1)
178156
*/
179157

180158
/* LSR register bits */
@@ -195,28 +173,19 @@
195173

196174
/* MSR register bits */
197175
#define SC16IS7XX_MSR_DCTS_BIT BIT(0) /* Delta CTS Clear To Send */
198-
#define SC16IS7XX_MSR_DDSR_BIT BIT(1) /* Delta DSR Data Set Ready
199-
* or (IO4)
176+
#define SC16IS7XX_MSR_DDSR_BIT BIT(1) /* Delta DSR Data Set Ready or (IO4)
200177
* - only on 75x/76x
201178
*/
202-
#define SC16IS7XX_MSR_DRI_BIT BIT(2) /* Delta RI Ring Indicator
203-
* or (IO7)
179+
#define SC16IS7XX_MSR_DRI_BIT BIT(2) /* Delta RI Ring Indicator or (IO7)
204180
* - only on 75x/76x
205181
*/
206-
#define SC16IS7XX_MSR_DCD_BIT BIT(3) /* Delta CD Carrier Detect
207-
* or (IO6)
182+
#define SC16IS7XX_MSR_DCD_BIT BIT(3) /* Delta CD Carrier Detect or (IO6)
208183
* - only on 75x/76x
209184
*/
210185
#define SC16IS7XX_MSR_CTS_BIT BIT(4) /* CTS */
211-
#define SC16IS7XX_MSR_DSR_BIT BIT(5) /* DSR (IO4)
212-
* - only on 75x/76x
213-
*/
214-
#define SC16IS7XX_MSR_RI_BIT BIT(6) /* RI (IO7)
215-
* - only on 75x/76x
216-
*/
217-
#define SC16IS7XX_MSR_CD_BIT BIT(7) /* CD (IO6)
218-
* - only on 75x/76x
219-
*/
186+
#define SC16IS7XX_MSR_DSR_BIT BIT(5) /* DSR (IO4) - only on 75x/76x */
187+
#define SC16IS7XX_MSR_RI_BIT BIT(6) /* RI (IO7) - only on 75x/76x */
188+
#define SC16IS7XX_MSR_CD_BIT BIT(7) /* CD (IO6) - only on 75x/76x */
220189

221190
/*
222191
* TCR register bits
@@ -255,54 +224,42 @@
255224
#define SC16IS7XX_IOCONTROL_SRESET_BIT BIT(3) /* Software Reset */
256225

257226
/* EFCR register bits */
258-
#define SC16IS7XX_EFCR_9BIT_MODE_BIT BIT(0) /* Enable 9-bit or Multidrop
259-
* mode (RS485) */
227+
#define SC16IS7XX_EFCR_9BIT_MODE_BIT BIT(0) /* Enable 9-bit or Multidrop mode (RS485) */
260228
#define SC16IS7XX_EFCR_RXDISABLE_BIT BIT(1) /* Disable receiver */
261229
#define SC16IS7XX_EFCR_TXDISABLE_BIT BIT(2) /* Disable transmitter */
262230
#define SC16IS7XX_EFCR_AUTO_RS485_BIT BIT(4) /* Auto RS485 RTS direction */
263231
#define SC16IS7XX_EFCR_RTS_INVERT_BIT BIT(5) /* RTS output inversion */
264232
#define SC16IS7XX_EFCR_IRDA_MODE_BIT BIT(7) /* IrDA mode
265-
* 0 = rate upto 115.2 kbit/s
266-
* - Only 75x/76x
267-
* 1 = rate upto 1.152 Mbit/s
268-
* - Only 76x
233+
* 0 = rate up to 115.2 kbit/s - Only 75x/76x
234+
* 1 = rate up to 1.152 Mbit/s - Only 76x
269235
*/
270236

271237
/* EFR register bits */
272238
#define SC16IS7XX_EFR_AUTORTS_BIT BIT(6) /* Auto RTS flow ctrl enable */
273239
#define SC16IS7XX_EFR_AUTOCTS_BIT BIT(7) /* Auto CTS flow ctrl enable */
274240
#define SC16IS7XX_EFR_XOFF2_DETECT_BIT BIT(5) /* Enable Xoff2 detection */
275-
#define SC16IS7XX_EFR_ENABLE_BIT BIT(4) /* Enable enhanced functions
276-
* and writing to IER[7:4],
277-
* FCR[5:4], MCR[7:5]
241+
#define SC16IS7XX_EFR_ENABLE_BIT BIT(4) /* Enable enhanced functions and writing to
242+
* IER[7:4], FCR[5:4], MCR[7:5]
278243
*/
279244
#define SC16IS7XX_EFR_SWFLOW3_BIT BIT(3)
280245
#define SC16IS7XX_EFR_SWFLOW2_BIT BIT(2)
281246
/*
282247
* SWFLOW bits 3 & 2 table:
283-
* 00 -> no transmitter flow
284-
* control
285-
* 01 -> transmitter generates
286-
* XON2 and XOFF2
287-
* 10 -> transmitter generates
288-
* XON1 and XOFF1
289-
* 11 -> transmitter generates
290-
* XON1, XON2, XOFF1 and
291-
* XOFF2
248+
* 00 -> no transmitter flow control
249+
* 01 -> transmitter generates XON2 and XOFF2
250+
* 10 -> transmitter generates XON1 and XOFF1
251+
* 11 -> transmitter generates XON1, XON2,
252+
* XOFF1 and XOFF2
292253
*/
293254
#define SC16IS7XX_EFR_SWFLOW1_BIT BIT(1)
294255
#define SC16IS7XX_EFR_SWFLOW0_BIT BIT(0)
295256
/*
296257
* SWFLOW bits 1 & 0 table:
297-
* 00 -> no received flow
298-
* control
299-
* 01 -> receiver compares
300-
* XON2 and XOFF2
301-
* 10 -> receiver compares
302-
* XON1 and XOFF1
303-
* 11 -> receiver compares
304-
* XON1, XON2, XOFF1 and
305-
* XOFF2
258+
* 00 -> no received flow control
259+
* 01 -> receiver compares XON2 and XOFF2
260+
* 10 -> receiver compares XON1 and XOFF1
261+
* 11 -> receiver compares XON1, XON2,
262+
* XOFF1 and XOFF2
306263
*/
307264
#define SC16IS7XX_EFR_FLOWCTRL_BITS (SC16IS7XX_EFR_AUTORTS_BIT | \
308265
SC16IS7XX_EFR_AUTOCTS_BIT | \
@@ -1152,7 +1109,7 @@ static int sc16is7xx_startup(struct uart_port *port)
11521109

11531110
sc16is7xx_power(port, 1);
11541111

1155-
/* Reset FIFOs*/
1112+
/* Reset FIFOs */
11561113
val = SC16IS7XX_FCR_RXRESET_BIT | SC16IS7XX_FCR_TXRESET_BIT;
11571114
sc16is7xx_port_write(port, SC16IS7XX_FCR_REG, val);
11581115
udelay(5);

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