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chewittsuperna9999
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drm/meson: fix colour distortion from HDR set during vendor u-boot
Add support for the OSD1 HDR registers so meson DRM can handle the HDR properties set by Amlogic u-boot on G12A and newer devices which result in blue/green/pink colour distortion to display output. This takes the original patch submissions from Mathias [0] and [1] with corrections for formatting and the missing description and attribution needed for merge. [0] https://lore.kernel.org/linux-amlogic/59dfd7e6-fc91-3d61-04c4-94e078a3188c@baylibre.com/T/ [1] https://lore.kernel.org/linux-amlogic/CAOKfEHBx_fboUqkENEMd-OC-NSrf46nto+vDLgvgttzPe99kXg@mail.gmail.com/T/#u Fixes: 7288839 ("drm/meson: Add G12A Support for VIU setup") Suggested-by: Mathias Steiger <mathias.steiger@googlemail.com> Signed-off-by: Christian Hewitt <christianshewitt@gmail.com> Tested-by: Neil Armstrong <narmstrong@baylibre.com> Tested-by: Philip Milev <milev.philip@gmail.com> [narmsrong: adding missing space on second tested-by tag] Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210806094005.7136-1-christianshewitt@gmail.com
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Lines changed: 11 additions & 1 deletion

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drivers/gpu/drm/meson/meson_registers.h

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@@ -634,6 +634,11 @@
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#define VPP_WRAP_OSD3_MATRIX_PRE_OFFSET2 0x3dbc
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#define VPP_WRAP_OSD3_MATRIX_EN_CTRL 0x3dbd
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/* osd1 HDR */
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#define OSD1_HDR2_CTRL 0x38a0
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#define OSD1_HDR2_CTRL_VDIN0_HDR2_TOP_EN BIT(13)
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#define OSD1_HDR2_CTRL_REG_ONLY_MAT BIT(16)
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/* osd2 scaler */
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#define OSD2_VSC_PHASE_STEP 0x3d00
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#define OSD2_VSC_INI_PHASE 0x3d01

drivers/gpu/drm/meson/meson_viu.c

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@@ -425,9 +425,14 @@ void meson_viu_init(struct meson_drm *priv)
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if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXM) ||
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meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXL))
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meson_viu_load_matrix(priv);
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else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A))
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else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) {
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meson_viu_set_g12a_osd1_matrix(priv, RGB709_to_YUV709l_coeff,
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true);
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/* fix green/pink color distortion from vendor u-boot */
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writel_bits_relaxed(OSD1_HDR2_CTRL_REG_ONLY_MAT |
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OSD1_HDR2_CTRL_VDIN0_HDR2_TOP_EN, 0,
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priv->io_base + _REG(OSD1_HDR2_CTRL));
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}
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/* Initialize OSD1 fifo control register */
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reg = VIU_OSD_DDR_PRIORITY_URGENT |

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