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AngeloGioacchino Del Regnorobherring
AngeloGioacchino Del Regno
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robherring
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dt-bindings: display: mediatek: Fix examples on new bindings
To avoid failure of dt_binding_check perform a slight refactoring of the examples: the main block is kept, but that required fixing the address and size cells, plus the inclusion of missing dt-bindings headers, required to parse some of the values assigned to various properties. Fixes: 4ed545e ("dt-bindings: display: mediatek: disp: split each block to individual yaml") Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com> Reviewed-by: Rob Herring <robh@kernel.org> Acked-by: Chun-Kuang Hu <chunkuang.hu@kernel.org> Tested-by: jason-jh.lin <jason-jh.lin@medaitek.com> Signed-off-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220309134702.9942-5-jason-jh.lin@mediatek.com
1 parent 10f17b2 commit bff4e30

17 files changed

Lines changed: 260 additions & 134 deletions

‎Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml‎

Lines changed: 16 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -66,12 +66,21 @@ additionalProperties: false
6666

6767
examples:
6868
- |
69+
#include <dt-bindings/interrupt-controller/arm-gic.h>
70+
#include <dt-bindings/clock/mt8173-clk.h>
71+
#include <dt-bindings/power/mt8173-power.h>
72+
#include <dt-bindings/gce/mt8173-gce.h>
6973
70-
aal@14015000 {
71-
compatible = "mediatek,mt8173-disp-aal";
72-
reg = <0 0x14015000 0 0x1000>;
73-
interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_LOW>;
74-
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
75-
clocks = <&mmsys CLK_MM_DISP_AAL>;
76-
mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>;
74+
soc {
75+
#address-cells = <2>;
76+
#size-cells = <2>;
77+
78+
aal@14015000 {
79+
compatible = "mediatek,mt8173-disp-aal";
80+
reg = <0 0x14015000 0 0x1000>;
81+
interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_LOW>;
82+
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
83+
clocks = <&mmsys CLK_MM_DISP_AAL>;
84+
mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>;
85+
};
7786
};

‎Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml‎

Lines changed: 16 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -65,12 +65,21 @@ additionalProperties: false
6565

6666
examples:
6767
- |
68+
#include <dt-bindings/interrupt-controller/arm-gic.h>
69+
#include <dt-bindings/clock/mt8183-clk.h>
70+
#include <dt-bindings/power/mt8183-power.h>
71+
#include <dt-bindings/gce/mt8183-gce.h>
6872
69-
ccorr0: ccorr@1400f000 {
70-
compatible = "mediatek,mt8183-disp-ccorr";
71-
reg = <0 0x1400f000 0 0x1000>;
72-
interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>;
73-
power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
74-
clocks = <&mmsys CLK_MM_DISP_CCORR0>;
75-
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>;
73+
soc {
74+
#address-cells = <2>;
75+
#size-cells = <2>;
76+
77+
ccorr0: ccorr@1400f000 {
78+
compatible = "mediatek,mt8183-disp-ccorr";
79+
reg = <0 0x1400f000 0 0x1000>;
80+
interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>;
81+
power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
82+
clocks = <&mmsys CLK_MM_DISP_CCORR0>;
83+
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>;
84+
};
7685
};

‎Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml‎

Lines changed: 16 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -75,12 +75,21 @@ additionalProperties: false
7575

7676
examples:
7777
- |
78+
#include <dt-bindings/interrupt-controller/arm-gic.h>
79+
#include <dt-bindings/clock/mt8173-clk.h>
80+
#include <dt-bindings/power/mt8173-power.h>
81+
#include <dt-bindings/gce/mt8173-gce.h>
7882
79-
color0: color@14013000 {
80-
compatible = "mediatek,mt8173-disp-color";
81-
reg = <0 0x14013000 0 0x1000>;
82-
interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_LOW>;
83-
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
84-
clocks = <&mmsys CLK_MM_DISP_COLOR0>;
85-
mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x3000 0x1000>;
83+
soc {
84+
#address-cells = <2>;
85+
#size-cells = <2>;
86+
87+
color0: color@14013000 {
88+
compatible = "mediatek,mt8173-disp-color";
89+
reg = <0 0x14013000 0 0x1000>;
90+
interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_LOW>;
91+
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
92+
clocks = <&mmsys CLK_MM_DISP_COLOR0>;
93+
mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x3000 0x1000>;
94+
};
8695
};

‎Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml‎

Lines changed: 16 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -65,12 +65,21 @@ additionalProperties: false
6565

6666
examples:
6767
- |
68+
#include <dt-bindings/interrupt-controller/arm-gic.h>
69+
#include <dt-bindings/clock/mt8183-clk.h>
70+
#include <dt-bindings/power/mt8183-power.h>
71+
#include <dt-bindings/gce/mt8183-gce.h>
6872
69-
dither0: dither@14012000 {
70-
compatible = "mediatek,mt8183-disp-dither";
71-
reg = <0 0x14012000 0 0x1000>;
72-
interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_LOW>;
73-
power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
74-
clocks = <&mmsys CLK_MM_DISP_DITHER0>;
75-
mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>;
73+
soc {
74+
#address-cells = <2>;
75+
#size-cells = <2>;
76+
77+
dither0: dither@14012000 {
78+
compatible = "mediatek,mt8183-disp-dither";
79+
reg = <0 0x14012000 0 0x1000>;
80+
interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_LOW>;
81+
power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
82+
clocks = <&mmsys CLK_MM_DISP_DITHER0>;
83+
mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>;
84+
};
7685
};

‎Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml‎

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -70,8 +70,7 @@ examples:
7070
- |
7171
#include <dt-bindings/interrupt-controller/arm-gic.h>
7272
#include <dt-bindings/clock/mt8173-clk.h>
73-
#include <dt-bindings/interrupt-controller/arm-gic.h>
74-
#include <dt-bindings/interrupt-controller/irq.h>
73+
7574
dpi0: dpi@1401d000 {
7675
compatible = "mediatek,mt8173-dpi";
7776
reg = <0x1401d000 0x1000>;

‎Documentation/devicetree/bindings/display/mediatek/mediatek,dsc.yaml‎

Lines changed: 16 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -60,12 +60,21 @@ additionalProperties: false
6060

6161
examples:
6262
- |
63+
#include <dt-bindings/interrupt-controller/arm-gic.h>
64+
#include <dt-bindings/clock/mt8195-clk.h>
65+
#include <dt-bindings/power/mt8195-power.h>
66+
#include <dt-bindings/gce/mt8195-gce.h>
6367
64-
dsc0: disp_dsc_wrap@1c009000 {
65-
compatible = "mediatek,mt8195-disp-dsc";
66-
reg = <0 0x1c009000 0 0x1000>;
67-
interrupts = <GIC_SPI 645 IRQ_TYPE_LEVEL_HIGH 0>;
68-
power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
69-
clocks = <&vdosys0 CLK_VDO0_DSC_WRAP0>;
70-
mediatek,gce-client-reg = <&gce1 SUBSYS_1c00XXXX 0x9000 0x1000>;
68+
soc {
69+
#address-cells = <2>;
70+
#size-cells = <2>;
71+
72+
dsc0: disp_dsc_wrap@1c009000 {
73+
compatible = "mediatek,mt8195-disp-dsc";
74+
reg = <0 0x1c009000 0 0x1000>;
75+
interrupts = <GIC_SPI 645 IRQ_TYPE_LEVEL_HIGH 0>;
76+
power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
77+
clocks = <&vdosys0 CLK_VDO0_DSC_WRAP0>;
78+
mediatek,gce-client-reg = <&gce1 SUBSYS_1c00XXXX 0x9000 0x1000>;
79+
};
7180
};

‎Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml‎

Lines changed: 16 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -66,12 +66,21 @@ additionalProperties: false
6666

6767
examples:
6868
- |
69+
#include <dt-bindings/interrupt-controller/arm-gic.h>
70+
#include <dt-bindings/clock/mt8173-clk.h>
71+
#include <dt-bindings/power/mt8173-power.h>
72+
#include <dt-bindings/gce/mt8173-gce.h>
6973
70-
gamma@14016000 {
71-
compatible = "mediatek,mt8173-disp-gamma";
72-
reg = <0 0x14016000 0 0x1000>;
73-
interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_LOW>;
74-
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
75-
clocks = <&mmsys CLK_MM_DISP_GAMMA>;
76-
mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x6000 0x1000>;
74+
soc {
75+
#address-cells = <2>;
76+
#size-cells = <2>;
77+
78+
gamma@14016000 {
79+
compatible = "mediatek,mt8173-disp-gamma";
80+
reg = <0 0x14016000 0 0x1000>;
81+
interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_LOW>;
82+
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
83+
clocks = <&mmsys CLK_MM_DISP_GAMMA>;
84+
mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x6000 0x1000>;
85+
};
7786
};

‎Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml‎

Lines changed: 22 additions & 27 deletions
Original file line numberDiff line numberDiff line change
@@ -38,18 +38,16 @@ properties:
3838
Documentation/devicetree/bindings/power/power-domain.yaml for details.
3939

4040
clocks:
41+
minItems: 1
4142
maxItems: 2
42-
items:
43-
- description: MERGE Clock
44-
- description: MERGE Async Clock
45-
Controlling the synchronous process between MERGE and other display
46-
function blocks cross clock domain.
4743

4844
clock-names:
49-
maxItems: 2
50-
items:
51-
- const: merge
52-
- const: merge_async
45+
oneOf:
46+
- items:
47+
- const: merge
48+
- items:
49+
- const: merge
50+
- const: merge_async
5351

5452
mediatek,merge-fifo-en:
5553
description:
@@ -88,23 +86,20 @@ additionalProperties: false
8886

8987
examples:
9088
- |
91-
92-
merge@14017000 {
93-
compatible = "mediatek,mt8173-disp-merge";
94-
reg = <0 0x14017000 0 0x1000>;
95-
power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
96-
clocks = <&mmsys CLK_MM_DISP_MERGE>;
89+
#include <dt-bindings/interrupt-controller/arm-gic.h>
90+
#include <dt-bindings/clock/mt8173-clk.h>
91+
#include <dt-bindings/power/mt8173-power.h>
92+
93+
soc {
94+
#address-cells = <2>;
95+
#size-cells = <2>;
96+
97+
merge@14017000 {
98+
compatible = "mediatek,mt8173-disp-merge";
99+
reg = <0 0x14017000 0 0x1000>;
100+
power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
101+
clocks = <&mmsys CLK_MM_DISP_MERGE>;
102+
clock-names = "merge";
103+
};
97104
};
98105
99-
merge5: disp_vpp_merge5@1c110000 {
100-
compatible = "mediatek,mt8195-disp-merge";
101-
reg = <0 0x1c110000 0 0x1000>;
102-
interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH 0>;
103-
clocks = <&vdosys1 CLK_VDO1_VPP_MERGE4>,
104-
<&vdosys1 CLK_VDO1_MERGE4_DL_ASYNC>;
105-
clock-names = "merge","merge_async";
106-
power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
107-
mediatek,gce-client-reg = <&gce1 SUBSYS_1c11XXXX 0x0000 0x1000>;
108-
mediatek,merge-fifo-en = <1>;
109-
resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE4_DL_ASYNC>;
110-
};

‎Documentation/devicetree/bindings/display/mediatek/mediatek,mutex.yaml‎

Lines changed: 17 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -71,13 +71,22 @@ additionalProperties: false
7171

7272
examples:
7373
- |
74+
#include <dt-bindings/interrupt-controller/arm-gic.h>
75+
#include <dt-bindings/clock/mt8173-clk.h>
76+
#include <dt-bindings/power/mt8173-power.h>
77+
#include <dt-bindings/gce/mt8173-gce.h>
7478
75-
mutex: mutex@14020000 {
76-
compatible = "mediatek,mt8173-disp-mutex";
77-
reg = <0 0x14020000 0 0x1000>;
78-
interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>;
79-
power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
80-
clocks = <&mmsys CLK_MM_MUTEX_32K>;
81-
mediatek,gce-events = <CMDQ_EVENT_MUTEX0_STREAM_EOF>,
82-
<CMDQ_EVENT_MUTEX1_STREAM_EOF>;
79+
soc {
80+
#address-cells = <2>;
81+
#size-cells = <2>;
82+
83+
mutex: mutex@14020000 {
84+
compatible = "mediatek,mt8173-disp-mutex";
85+
reg = <0 0x14020000 0 0x1000>;
86+
interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>;
87+
power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
88+
clocks = <&mmsys CLK_MM_MUTEX_32K>;
89+
mediatek,gce-events = <CMDQ_EVENT_MUTEX0_STREAM_EOF>,
90+
<CMDQ_EVENT_MUTEX1_STREAM_EOF>;
91+
};
8392
};

‎Documentation/devicetree/bindings/display/mediatek/mediatek,od.yaml‎

Lines changed: 10 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -45,9 +45,15 @@ additionalProperties: false
4545

4646
examples:
4747
- |
48+
#include <dt-bindings/clock/mt8173-clk.h>
4849
49-
od@14023000 {
50-
compatible = "mediatek,mt8173-disp-od";
51-
reg = <0 0x14023000 0 0x1000>;
52-
clocks = <&mmsys CLK_MM_DISP_OD>;
50+
soc {
51+
#address-cells = <2>;
52+
#size-cells = <2>;
53+
54+
od@14023000 {
55+
compatible = "mediatek,mt8173-disp-od";
56+
reg = <0 0x14023000 0 0x1000>;
57+
clocks = <&mmsys CLK_MM_DISP_OD>;
58+
};
5359
};

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