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Merge tag 'qcom-clk-for-6.19' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into clk-qcom
Pull Qualcomm clk driver updates from Bjorn Andersson: - Qualcomm IPQ5424 Network Subsystem Clock Controller - Qualcomm SM8750 Video Clock Controller - Describe parent/child relationship among the Qualcomm Titan GDSCs on SM845, SM6350, SM7150, SM8250, SM8450, and SM8550 - Define display subsystem reset signals for SM6350, SM7150, and SDM660 - Add missing USB4 clocks and resets on Hamoa - Address a variety of smaller issues across the drivers, and a few more Kconfig dependency issues * tag 'qcom-clk-for-6.19' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (47 commits) clk: qcom: x1e80100-dispcc: Add USB4 router link resets dt-bindings: clock: qcom: x1e80100-dispcc: Add USB4 router link resets clk: qcom: videocc-sm8750: Add video clock controller driver for SM8750 dt-bindings: clock: qcom: Add SM8750 video clock controller clk: qcom: branch: Extend invert logic for branch2 mem clocks clk: qcom: ecpricc-qdu100: Add mem_enable_mask to the clock memory branch clk: qcom: clk_mem_branch: add enable mask and invert flags clk: qcom: mmcc-sdm660: Add missing MDSS reset dt-bindings: clock: mmcc-sdm660: Add missing MDSS reset clk: qcom: use different Kconfig prompts for APSS IPQ5424/6018 drivers clk: qcom: apss-ipq5424: remove unused 'apss_clk' structure dt-bindings: clock: qcom: Add Kaanapali Global clock controller dt-bindings: clock: qcom: Document the Kaanapali TCSR Clock Controller dt-bindings: clock: qcom-rpmhcc: Add RPMHCC for Kaanapali clk: qcom: tcsrcc-glymur: Update register offsets for clock refs clk: qcom: gcc-qcs615: Update the SDCC clock to use shared_floor_ops clk: qcom: camcc-sm7150: Fix PLL config of PLL2 clk: qcom: camcc-sm6350: Fix PLL config of PLL2 clk: qcom: Add NSS clock controller driver for IPQ5424 clk: qcom: gcc-ipq5424: Add gpll0_out_aux clock ...
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43 files changed

Lines changed: 3298 additions & 104 deletions

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‎Documentation/devicetree/bindings/clock/qcom,ipq9574-nsscc.yaml‎

Lines changed: 55 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -4,29 +4,37 @@
44
$id: http://devicetree.org/schemas/clock/qcom,ipq9574-nsscc.yaml#
55
$schema: http://devicetree.org/meta-schemas/core.yaml#
66

7-
title: Qualcomm Networking Sub System Clock & Reset Controller on IPQ9574
7+
title: Qualcomm Networking Sub System Clock & Reset Controller on IPQ9574 and IPQ5424
88

99
maintainers:
1010
- Bjorn Andersson <andersson@kernel.org>
1111
- Anusha Rao <quic_anusha@quicinc.com>
1212

1313
description: |
1414
Qualcomm networking sub system clock control module provides the clocks,
15-
resets on IPQ9574
15+
resets on IPQ9574 and IPQ5424
1616
17-
See also::
17+
See also:
18+
include/dt-bindings/clock/qcom,ipq5424-nsscc.h
1819
include/dt-bindings/clock/qcom,ipq9574-nsscc.h
20+
include/dt-bindings/reset/qcom,ipq5424-nsscc.h
1921
include/dt-bindings/reset/qcom,ipq9574-nsscc.h
2022
2123
properties:
2224
compatible:
23-
const: qcom,ipq9574-nsscc
25+
enum:
26+
- qcom,ipq5424-nsscc
27+
- qcom,ipq9574-nsscc
2428

2529
clocks:
2630
items:
2731
- description: Board XO source
28-
- description: CMN_PLL NSS 1200MHz (Bias PLL cc) clock source
29-
- description: CMN_PLL PPE 353MHz (Bias PLL ubi nc) clock source
32+
- description: CMN_PLL NSS (Bias PLL cc) clock source. This clock rate
33+
can vary for different IPQ SoCs. For example, it is 1200 MHz on the
34+
IPQ9574 and 300 MHz on the IPQ5424.
35+
- description: CMN_PLL PPE (Bias PLL ubi nc) clock source. The clock
36+
rate can vary for different IPQ SoCs. For example, it is 353 MHz
37+
on the IPQ9574 and 375 MHz on the IPQ5424.
3038
- description: GCC GPLL0 OUT AUX clock source
3139
- description: Uniphy0 NSS Rx clock source
3240
- description: Uniphy0 NSS Tx clock source
@@ -42,8 +50,12 @@ properties:
4250
clock-names:
4351
items:
4452
- const: xo
45-
- const: nss_1200
46-
- const: ppe_353
53+
- enum:
54+
- nss_1200
55+
- nss
56+
- enum:
57+
- ppe_353
58+
- ppe
4759
- const: gpll0_out
4860
- const: uniphy0_rx
4961
- const: uniphy0_tx
@@ -60,6 +72,40 @@ required:
6072

6173
allOf:
6274
- $ref: qcom,gcc.yaml#
75+
- if:
76+
properties:
77+
compatible:
78+
const: qcom,ipq9574-nsscc
79+
then:
80+
properties:
81+
clock-names:
82+
items:
83+
- const: xo
84+
- const: nss_1200
85+
- const: ppe_353
86+
- const: gpll0_out
87+
- const: uniphy0_rx
88+
- const: uniphy0_tx
89+
- const: uniphy1_rx
90+
- const: uniphy1_tx
91+
- const: uniphy2_rx
92+
- const: uniphy2_tx
93+
- const: bus
94+
else:
95+
properties:
96+
clock-names:
97+
items:
98+
- const: xo
99+
- const: nss
100+
- const: ppe
101+
- const: gpll0_out
102+
- const: uniphy0_rx
103+
- const: uniphy0_tx
104+
- const: uniphy1_rx
105+
- const: uniphy1_tx
106+
- const: uniphy2_rx
107+
- const: uniphy2_tx
108+
- const: bus
63109

64110
unevaluatedProperties: false
65111

@@ -94,5 +140,6 @@ examples:
94140
"bus";
95141
#clock-cells = <1>;
96142
#reset-cells = <1>;
143+
#interconnect-cells = <1>;
97144
};
98145
...

‎Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -18,6 +18,7 @@ properties:
1818
compatible:
1919
enum:
2020
- qcom,glymur-rpmh-clk
21+
- qcom,kaanapali-rpmh-clk
2122
- qcom,milos-rpmh-clk
2223
- qcom,qcs615-rpmh-clk
2324
- qcom,qdu1000-rpmh-clk

‎Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml‎

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
77
title: Qualcomm Video Clock & Reset Controller on SM8450
88

99
maintainers:
10-
- Taniya Das <quic_tdas@quicinc.com>
10+
- Taniya Das <taniya.das@oss.qualcomm.com>
1111
- Jagadeesh Kona <quic_jkona@quicinc.com>
1212

1313
description: |
@@ -17,6 +17,7 @@ description: |
1717
See also:
1818
include/dt-bindings/clock/qcom,sm8450-videocc.h
1919
include/dt-bindings/clock/qcom,sm8650-videocc.h
20+
include/dt-bindings/clock/qcom,sm8750-videocc.h
2021
2122
properties:
2223
compatible:
@@ -25,6 +26,7 @@ properties:
2526
- qcom,sm8475-videocc
2627
- qcom,sm8550-videocc
2728
- qcom,sm8650-videocc
29+
- qcom,sm8750-videocc
2830
- qcom,x1e80100-videocc
2931

3032
clocks:
@@ -61,6 +63,7 @@ allOf:
6163
enum:
6264
- qcom,sm8450-videocc
6365
- qcom,sm8550-videocc
66+
- qcom,sm8750-videocc
6467
then:
6568
required:
6669
- required-opps

‎Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -25,6 +25,7 @@ properties:
2525
items:
2626
- enum:
2727
- qcom,glymur-tcsr
28+
- qcom,kaanapali-tcsr
2829
- qcom,milos-tcsr
2930
- qcom,sar2130p-tcsr
3031
- qcom,sm8550-tcsr

‎Documentation/devicetree/bindings/clock/qcom,sm8750-gcc.yaml‎

Lines changed: 6 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -13,11 +13,15 @@ description: |
1313
Qualcomm global clock control module provides the clocks, resets and power
1414
domains on SM8750
1515
16-
See also: include/dt-bindings/clock/qcom,sm8750-gcc.h
16+
See also:
17+
include/dt-bindings/clock/qcom,kaanapali-gcc.h
18+
include/dt-bindings/clock/qcom,sm8750-gcc.h
1719
1820
properties:
1921
compatible:
20-
const: qcom,sm8750-gcc
22+
enum:
23+
- qcom,kaanapali-gcc
24+
- qcom,sm8750-gcc
2125

2226
clocks:
2327
items:

‎Documentation/devicetree/bindings/clock/qcom,x1e80100-gcc.yaml‎

Lines changed: 58 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -32,9 +32,36 @@ properties:
3232
- description: PCIe 5 pipe clock
3333
- description: PCIe 6a pipe clock
3434
- description: PCIe 6b pipe clock
35-
- description: USB QMP Phy 0 clock source
36-
- description: USB QMP Phy 1 clock source
37-
- description: USB QMP Phy 2 clock source
35+
- description: USB4_0 QMPPHY clock source
36+
- description: USB4_1 QMPPHY clock source
37+
- description: USB4_2 QMPPHY clock source
38+
- description: USB4_0 PHY DP0 GMUX clock source
39+
- description: USB4_0 PHY DP1 GMUX clock source
40+
- description: USB4_0 PHY PCIE PIPEGMUX clock source
41+
- description: USB4_0 PHY PIPEGMUX clock source
42+
- description: USB4_0 PHY SYS PCIE PIPEGMUX clock source
43+
- description: USB4_1 PHY DP0 GMUX 2 clock source
44+
- description: USB4_1 PHY DP1 GMUX 2 clock source
45+
- description: USB4_1 PHY PCIE PIPEGMUX clock source
46+
- description: USB4_1 PHY PIPEGMUX clock source
47+
- description: USB4_1 PHY SYS PCIE PIPEGMUX clock source
48+
- description: USB4_2 PHY DP0 GMUX 2 clock source
49+
- description: USB4_2 PHY DP1 GMUX 2 clock source
50+
- description: USB4_2 PHY PCIE PIPEGMUX clock source
51+
- description: USB4_2 PHY PIPEGMUX clock source
52+
- description: USB4_2 PHY SYS PCIE PIPEGMUX clock source
53+
- description: USB4_0 PHY RX 0 clock source
54+
- description: USB4_0 PHY RX 1 clock source
55+
- description: USB4_1 PHY RX 0 clock source
56+
- description: USB4_1 PHY RX 1 clock source
57+
- description: USB4_2 PHY RX 0 clock source
58+
- description: USB4_2 PHY RX 1 clock source
59+
- description: USB4_0 PHY PCIE PIPE clock source
60+
- description: USB4_0 PHY max PIPE clock source
61+
- description: USB4_1 PHY PCIE PIPE clock source
62+
- description: USB4_1 PHY max PIPE clock source
63+
- description: USB4_2 PHY PCIE PIPE clock source
64+
- description: USB4_2 PHY max PIPE clock source
3865

3966
power-domains:
4067
description:
@@ -67,7 +94,34 @@ examples:
6794
<&pcie6b_phy>,
6895
<&usb_1_ss0_qmpphy 0>,
6996
<&usb_1_ss1_qmpphy 1>,
70-
<&usb_1_ss2_qmpphy 2>;
97+
<&usb_1_ss2_qmpphy 2>,
98+
<&usb4_0_phy_dp0_gmux_clk>,
99+
<&usb4_0_phy_dp1_gmux_clk>,
100+
<&usb4_0_phy_pcie_pipegmux_clk>,
101+
<&usb4_0_phy_pipegmux_clk>,
102+
<&usb4_0_phy_sys_pcie_pipegmux_clk>,
103+
<&usb4_1_phy_dp0_gmux_2_clk>,
104+
<&usb4_1_phy_dp1_gmux_2_clk>,
105+
<&usb4_1_phy_pcie_pipegmux_clk>,
106+
<&usb4_1_phy_pipegmux_clk>,
107+
<&usb4_1_phy_sys_pcie_pipegmux_clk>,
108+
<&usb4_2_phy_dp0_gmux_2_clk>,
109+
<&usb4_2_phy_dp1_gmux_2_clk>,
110+
<&usb4_2_phy_pcie_pipegmux_clk>,
111+
<&usb4_2_phy_pipegmux_clk>,
112+
<&usb4_2_phy_sys_pcie_pipegmux_clk>,
113+
<&usb4_0_phy_rx_0_clk>,
114+
<&usb4_0_phy_rx_1_clk>,
115+
<&usb4_1_phy_rx_0_clk>,
116+
<&usb4_1_phy_rx_1_clk>,
117+
<&usb4_2_phy_rx_0_clk>,
118+
<&usb4_2_phy_rx_1_clk>,
119+
<&usb4_0_phy_pcie_pipe_clk>,
120+
<&usb4_0_phy_max_pipe_clk>,
121+
<&usb4_1_phy_pcie_pipe_clk>,
122+
<&usb4_1_phy_max_pipe_clk>,
123+
<&usb4_2_phy_pcie_pipe_clk>,
124+
<&usb4_2_phy_max_pipe_clk>;
71125
power-domains = <&rpmhpd RPMHPD_CX>;
72126
#clock-cells = <1>;
73127
#reset-cells = <1>;

‎drivers/clk/qcom/Kconfig‎

Lines changed: 29 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -215,16 +215,16 @@ config IPQ_APSS_PLL
215215
devices.
216216

217217
config IPQ_APSS_5424
218-
tristate "IPQ APSS Clock Controller"
218+
tristate "IPQ5424 APSS Clock Controller"
219219
select IPQ_APSS_PLL
220220
default y if IPQ_GCC_5424
221221
help
222-
Support for APSS Clock controller on Qualcom IPQ5424 platform.
222+
Support for APSS Clock controller on Qualcomm IPQ5424 platform.
223223
Say Y if you want to support CPU frequency scaling on ipq based
224224
devices.
225225

226226
config IPQ_APSS_6018
227-
tristate "IPQ APSS Clock Controller"
227+
tristate "IPQ6018 APSS Clock Controller"
228228
select IPQ_APSS_PLL
229229
depends on QCOM_APCS_IPC || COMPILE_TEST
230230
depends on QCOM_SMEM
@@ -317,6 +317,17 @@ config IPQ_GCC_9574
317317
i2c, USB, SD/eMMC, etc. Select this for the root clock
318318
of ipq9574.
319319

320+
config IPQ_NSSCC_5424
321+
tristate "IPQ5424 NSS Clock Controller"
322+
depends on ARM64 || COMPILE_TEST
323+
depends on IPQ_GCC_5424
324+
help
325+
Support for NSS clock controller on ipq5424 devices.
326+
NSSCC receives the clock sources from GCC, CMN PLL and UNIPHY (PCS).
327+
It in turn supplies the clocks and resets to the networking hardware.
328+
Say Y or M if you want to enable networking function on the
329+
IPQ5424 devices.
330+
320331
config IPQ_NSSCC_9574
321332
tristate "IPQ9574 NSS Clock Controller"
322333
depends on ARM64 || COMPILE_TEST
@@ -531,6 +542,7 @@ config QCM_DISPCC_2290
531542

532543
config QCS_DISPCC_615
533544
tristate "QCS615 Display Clock Controller"
545+
depends on ARM64 || COMPILE_TEST
534546
select QCS_GCC_615
535547
help
536548
Support for the display clock controller on Qualcomm Technologies, Inc
@@ -586,6 +598,7 @@ config QCS_GCC_615
586598

587599
config QCS_GPUCC_615
588600
tristate "QCS615 Graphics clock controller"
601+
depends on ARM64 || COMPILE_TEST
589602
select QCS_GCC_615
590603
help
591604
Support for the graphics clock controller on QCS615 devices.
@@ -594,6 +607,7 @@ config QCS_GPUCC_615
594607

595608
config QCS_VIDEOCC_615
596609
tristate "QCS615 Video Clock Controller"
610+
depends on ARM64 || COMPILE_TEST
597611
select QCS_GCC_615
598612
help
599613
Support for the video clock controller on QCS615 devices.
@@ -1448,6 +1462,7 @@ config SA_VIDEOCC_8775P
14481462

14491463
config SM_VIDEOCC_6350
14501464
tristate "SM6350 Video Clock Controller"
1465+
depends on ARM64 || COMPILE_TEST
14511466
select SM_GCC_6350
14521467
select QCOM_GDSC
14531468
help
@@ -1516,6 +1531,17 @@ config SM_VIDEOCC_8550
15161531
Say Y if you want to support video devices and functionality such as
15171532
video encode/decode.
15181533

1534+
config SM_VIDEOCC_8750
1535+
tristate "SM8750 Video Clock Controller"
1536+
depends on ARM64 || COMPILE_TEST
1537+
select SM_GCC_8750
1538+
select QCOM_GDSC
1539+
help
1540+
Support for the video clock controller on Qualcomm Technologies, Inc.
1541+
SM8750 devices.
1542+
Say Y if you want to support video devices and functionality such as
1543+
video encode/decode.
1544+
15191545
config SPMI_PMIC_CLKDIV
15201546
tristate "SPMI PMIC clkdiv Support"
15211547
depends on SPMI || COMPILE_TEST

‎drivers/clk/qcom/Makefile‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -43,6 +43,7 @@ obj-$(CONFIG_IPQ_GCC_6018) += gcc-ipq6018.o
4343
obj-$(CONFIG_IPQ_GCC_806X) += gcc-ipq806x.o
4444
obj-$(CONFIG_IPQ_GCC_8074) += gcc-ipq8074.o
4545
obj-$(CONFIG_IPQ_GCC_9574) += gcc-ipq9574.o
46+
obj-$(CONFIG_IPQ_NSSCC_5424) += nsscc-ipq5424.o
4647
obj-$(CONFIG_IPQ_NSSCC_9574) += nsscc-ipq9574.o
4748
obj-$(CONFIG_IPQ_LCC_806X) += lcc-ipq806x.o
4849
obj-$(CONFIG_IPQ_NSSCC_QCA8K) += nsscc-qca8k.o
@@ -184,6 +185,7 @@ obj-$(CONFIG_SM_VIDEOCC_8250) += videocc-sm8250.o
184185
obj-$(CONFIG_SM_VIDEOCC_8350) += videocc-sm8350.o
185186
obj-$(CONFIG_SM_VIDEOCC_8450) += videocc-sm8450.o
186187
obj-$(CONFIG_SM_VIDEOCC_8550) += videocc-sm8550.o
188+
obj-$(CONFIG_SM_VIDEOCC_8750) += videocc-sm8750.o
187189
obj-$(CONFIG_SM_VIDEOCC_MILOS) += videocc-milos.o
188190
obj-$(CONFIG_SPMI_PMIC_CLKDIV) += clk-spmi-pmic-div.o
189191
obj-$(CONFIG_KPSS_XCC) += kpss-xcc.o

‎drivers/clk/qcom/apss-ipq5424.c‎

Lines changed: 0 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -35,13 +35,6 @@ enum {
3535
P_L3_PLL,
3636
};
3737

38-
struct apss_clk {
39-
struct notifier_block cpu_clk_notifier;
40-
struct clk_hw *hw;
41-
struct device *dev;
42-
struct clk *l3_clk;
43-
};
44-
4538
static const struct alpha_pll_config apss_pll_config = {
4639
.l = 0x3b,
4740
.config_ctl_val = 0x08200920,

‎drivers/clk/qcom/camcc-sdm845.c‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1543,6 +1543,7 @@ static struct gdsc bps_gdsc = {
15431543
.name = "bps_gdsc",
15441544
},
15451545
.flags = HW_CTRL | POLL_CFG_GDSCR,
1546+
.parent = &titan_top_gdsc.pd,
15461547
.pwrsts = PWRSTS_OFF_ON,
15471548
};
15481549

@@ -1552,6 +1553,7 @@ static struct gdsc ipe_0_gdsc = {
15521553
.name = "ipe_0_gdsc",
15531554
},
15541555
.flags = HW_CTRL | POLL_CFG_GDSCR,
1556+
.parent = &titan_top_gdsc.pd,
15551557
.pwrsts = PWRSTS_OFF_ON,
15561558
};
15571559

@@ -1561,6 +1563,7 @@ static struct gdsc ipe_1_gdsc = {
15611563
.name = "ipe_1_gdsc",
15621564
},
15631565
.flags = HW_CTRL | POLL_CFG_GDSCR,
1566+
.parent = &titan_top_gdsc.pd,
15641567
.pwrsts = PWRSTS_OFF_ON,
15651568
};
15661569

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