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lima1002alexdeucher
lima1002
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alexdeucher
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drm/amd/swsmu: Update smu v14.0.0 headers to be 14.0.1 compatible
update ppsmc.h pmfw.h and driver_if.h for smu v14_0_1 Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: lima1002 <li.ma@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
1 parent 5b0cd09 commit c5b1ccf

6 files changed

Lines changed: 413 additions & 43 deletions

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‎drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0_0.h‎

Lines changed: 32 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -144,6 +144,37 @@ typedef struct {
144144
uint32_t MaxGfxClk;
145145
} DpmClocks_t;
146146

147+
//Freq in MHz
148+
//Voltage in milli volts with 2 fractional bits
149+
typedef struct {
150+
uint32_t DcfClocks[NUM_DCFCLK_DPM_LEVELS];
151+
uint32_t DispClocks[NUM_DISPCLK_DPM_LEVELS];
152+
uint32_t DppClocks[NUM_DPPCLK_DPM_LEVELS];
153+
uint32_t SocClocks[NUM_SOCCLK_DPM_LEVELS];
154+
uint32_t VClocks0[NUM_VCN_DPM_LEVELS];
155+
uint32_t VClocks1[NUM_VCN_DPM_LEVELS];
156+
uint32_t DClocks0[NUM_VCN_DPM_LEVELS];
157+
uint32_t DClocks1[NUM_VCN_DPM_LEVELS];
158+
uint32_t VPEClocks[NUM_VPE_DPM_LEVELS];
159+
uint32_t FclkClocks_Freq[NUM_FCLK_DPM_LEVELS];
160+
uint32_t FclkClocks_Voltage[NUM_FCLK_DPM_LEVELS];
161+
uint32_t SocVoltage[NUM_SOC_VOLTAGE_LEVELS];
162+
MemPstateTable_t MemPstateTable[NUM_MEM_PSTATE_LEVELS];
163+
164+
uint8_t NumDcfClkLevelsEnabled;
165+
uint8_t NumDispClkLevelsEnabled; //Applies to both Dispclk and Dppclk
166+
uint8_t NumSocClkLevelsEnabled;
167+
uint8_t Vcn0ClkLevelsEnabled; //Applies to both Vclk0 and Dclk0
168+
uint8_t Vcn1ClkLevelsEnabled; //Applies to both Vclk1 and Dclk1
169+
uint8_t VpeClkLevelsEnabled;
170+
uint8_t NumMemPstatesEnabled;
171+
uint8_t NumFclkLevelsEnabled;
172+
uint8_t spare;
173+
174+
uint32_t MinGfxClk;
175+
uint32_t MaxGfxClk;
176+
} DpmClocks_t_v14_0_1;
177+
147178
typedef struct {
148179
uint16_t CoreFrequency[16]; //Target core frequency [MHz]
149180
uint16_t CorePower[16]; //CAC calculated core power [mW]
@@ -224,7 +255,7 @@ typedef enum {
224255
#define TABLE_CUSTOM_DPM 2 // Called by Driver
225256
#define TABLE_BIOS_GPIO_CONFIG 3 // Called by BIOS
226257
#define TABLE_DPMCLOCKS 4 // Called by Driver and VBIOS
227-
#define TABLE_SPARE0 5 // Unused
258+
#define TABLE_MOMENTARY_PM 5 // Called by Tools
228259
#define TABLE_MODERN_STDBY 6 // Called by Tools for Modern Standby Log
229260
#define TABLE_SMU_METRICS 7 // Called by Driver and SMF/PMF
230261
#define TABLE_COUNT 8

‎drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v14_0_0_pmfw.h‎

Lines changed: 46 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -42,7 +42,7 @@
4242
#define FEATURE_EDC_BIT 7
4343
#define FEATURE_PLL_POWER_DOWN_BIT 8
4444
#define FEATURE_VDDOFF_BIT 9
45-
#define FEATURE_VCN_DPM_BIT 10
45+
#define FEATURE_VCN_DPM_BIT 10 /* this is for both VCN0 and VCN1 */
4646
#define FEATURE_DS_MPM_BIT 11
4747
#define FEATURE_FCLK_DPM_BIT 12
4848
#define FEATURE_SOCCLK_DPM_BIT 13
@@ -56,18 +56,18 @@
5656
#define FEATURE_DS_GFXCLK_BIT 21
5757
#define FEATURE_DS_SOCCLK_BIT 22
5858
#define FEATURE_DS_LCLK_BIT 23
59-
#define FEATURE_LOW_POWER_DCNCLKS_BIT 24 // for all DISP clks
59+
#define FEATURE_LOW_POWER_DCNCLKS_BIT 24
6060
#define FEATURE_DS_SHUBCLK_BIT 25
61-
#define FEATURE_SPARE0_BIT 26 //SPARE
61+
#define FEATURE_RESERVED0_BIT 26
6262
#define FEATURE_ZSTATES_BIT 27
6363
#define FEATURE_IOMMUL2_PG_BIT 28
6464
#define FEATURE_DS_FCLK_BIT 29
6565
#define FEATURE_DS_SMNCLK_BIT 30
6666
#define FEATURE_DS_MP1CLK_BIT 31
6767
#define FEATURE_WHISPER_MODE_BIT 32
6868
#define FEATURE_SMU_LOW_POWER_BIT 33
69-
#define FEATURE_SMART_L3_RINSER_BIT 34
70-
#define FEATURE_SPARE1_BIT 35 //SPARE
69+
#define FEATURE_RESERVED1_BIT 34 /* v14_0_0 SMART_L3_RINSER; v14_0_1 RESERVED1 */
70+
#define FEATURE_GFX_DEM_BIT 35 /* v14_0_0 SPARE; v14_0_1 GFX_DEM */
7171
#define FEATURE_PSI_BIT 36
7272
#define FEATURE_PROCHOT_BIT 37
7373
#define FEATURE_CPUOFF_BIT 38
@@ -77,11 +77,11 @@
7777
#define FEATURE_PERF_LIMIT_BIT 42
7878
#define FEATURE_CORE_DLDO_BIT 43
7979
#define FEATURE_DVO_BIT 44
80-
#define FEATURE_DS_VCN_BIT 45
80+
#define FEATURE_DS_VCN_BIT 45 /* v14_0_1 this is for both VCN0 and VCN1 */
8181
#define FEATURE_CPPC_BIT 46
8282
#define FEATURE_CPPC_PREFERRED_CORES 47
8383
#define FEATURE_DF_CSTATES_BIT 48
84-
#define FEATURE_SPARE2_BIT 49 //SPARE
84+
#define FEATURE_FAST_PSTATE_CLDO_BIT 49 /* v14_0_0 SPARE */
8585
#define FEATURE_ATHUB_PG_BIT 50
8686
#define FEATURE_VDDOFF_ECO_BIT 51
8787
#define FEATURE_ZSTATES_ECO_BIT 52
@@ -93,8 +93,8 @@
9393
#define FEATURE_DS_IPUCLK_BIT 58
9494
#define FEATURE_DS_VPECLK_BIT 59
9595
#define FEATURE_VPE_DPM_BIT 60
96-
#define FEATURE_SPARE_61 61
97-
#define FEATURE_FP_DIDT 62
96+
#define FEATURE_SMART_L3_RINSER_BIT 61 /* v14_0_0 SPARE*/
97+
#define FEATURE_PCC_BIT 62 /* v14_0_0 FP_DIDT v14_0_1 PCC_BIT */
9898
#define NUM_FEATURES 63
9999

100100
// Firmware Header/Footer
@@ -151,6 +151,43 @@ typedef struct {
151151
// MP1_EXT_SCRATCH7 = RTOS Current Job
152152
} FwStatus_t;
153153

154+
typedef struct {
155+
// MP1_EXT_SCRATCH0
156+
uint32_t DpmHandlerID : 8;
157+
uint32_t ActivityMonitorID : 8;
158+
uint32_t DpmTimerID : 8;
159+
uint32_t DpmHubID : 4;
160+
uint32_t DpmHubTask : 4;
161+
// MP1_EXT_SCRATCH1
162+
uint32_t CclkSyncStatus : 8;
163+
uint32_t ZstateStatus : 4;
164+
uint32_t Cpu1VddOff : 4;
165+
uint32_t DstateFun : 4;
166+
uint32_t DstateDev : 4;
167+
uint32_t GfxOffStatus : 2;
168+
uint32_t Cpu0Off : 2;
169+
uint32_t Cpu1Off : 2;
170+
uint32_t Cpu0VddOff : 2;
171+
// MP1_EXT_SCRATCH2
172+
uint32_t P2JobHandler :32;
173+
// MP1_EXT_SCRATCH3
174+
uint32_t PostCode :32;
175+
// MP1_EXT_SCRATCH4
176+
uint32_t MsgPortBusy :15;
177+
uint32_t RsmuPmiP1Pending : 1;
178+
uint32_t RsmuPmiP2PendingCnt : 8;
179+
uint32_t DfCstateExitPending : 1;
180+
uint32_t Pc6EntryPending : 1;
181+
uint32_t Pc6ExitPending : 1;
182+
uint32_t WarmResetPending : 1;
183+
uint32_t Mp0ClkPending : 1;
184+
uint32_t InWhisperMode : 1;
185+
uint32_t spare2 : 2;
186+
// MP1_EXT_SCRATCH5
187+
uint32_t IdleMask :32;
188+
// MP1_EXT_SCRATCH6 = RTOS threads' status
189+
// MP1_EXT_SCRATCH7 = RTOS Current Job
190+
} FwStatus_t_v14_0_1;
154191

155192
#pragma pack(pop)
156193

‎drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v14_0_0_ppsmc.h‎

Lines changed: 8 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -72,23 +72,19 @@
7272
#define PPSMC_MSG_SetHardMinSocclkByFreq 0x13 ///< Set hard min for SOC CLK
7373
#define PPSMC_MSG_SetSoftMinFclk 0x14 ///< Set hard min for FCLK
7474
#define PPSMC_MSG_SetSoftMinVcn0 0x15 ///< Set soft min for VCN0 clocks (VCLK0 and DCLK0)
75-
7675
#define PPSMC_MSG_EnableGfxImu 0x16 ///< Enable GFX IMU
77-
78-
#define PPSMC_MSG_spare_0x17 0x17
79-
#define PPSMC_MSG_spare_0x18 0x18
76+
#define PPSMC_MSG_spare_0x17 0x17 ///< Get GFX clock frequency
77+
#define PPSMC_MSG_spare_0x18 0x18 ///< Get FCLK frequency
8078
#define PPSMC_MSG_AllowGfxOff 0x19 ///< Inform PMFW of allowing GFXOFF entry
8179
#define PPSMC_MSG_DisallowGfxOff 0x1A ///< Inform PMFW of disallowing GFXOFF entry
8280
#define PPSMC_MSG_SetSoftMaxGfxClk 0x1B ///< Set soft max for GFX CLK
8381
#define PPSMC_MSG_SetHardMinGfxClk 0x1C ///< Set hard min for GFX CLK
84-
8582
#define PPSMC_MSG_SetSoftMaxSocclkByFreq 0x1D ///< Set soft max for SOC CLK
8683
#define PPSMC_MSG_SetSoftMaxFclkByFreq 0x1E ///< Set soft max for FCLK
8784
#define PPSMC_MSG_SetSoftMaxVcn0 0x1F ///< Set soft max for VCN0 clocks (VCLK0 and DCLK0)
88-
#define PPSMC_MSG_spare_0x20 0x20
85+
#define PPSMC_MSG_spare_0x20 0x20 ///< Set power limit percentage
8986
#define PPSMC_MSG_PowerDownJpeg0 0x21 ///< Power down Jpeg of VCN0
9087
#define PPSMC_MSG_PowerUpJpeg0 0x22 ///< Power up Jpeg of VCN0; VCN0 is power gated by default
91-
9288
#define PPSMC_MSG_SetHardMinFclkByFreq 0x23 ///< Set hard min for FCLK
9389
#define PPSMC_MSG_SetSoftMinSocclkByFreq 0x24 ///< Set soft min for SOC CLK
9490
#define PPSMC_MSG_AllowZstates 0x25 ///< Inform PMFM of allowing Zstate entry, i.e. no Miracast activity
@@ -99,8 +95,8 @@
9995
#define PPSMC_MSG_PowerUpIspByTile 0x2A ///< This message is used to power up ISP tiles and enable the ISP DPM
10096
#define PPSMC_MSG_SetHardMinIspiclkByFreq 0x2B ///< Set HardMin by frequency for ISPICLK
10197
#define PPSMC_MSG_SetHardMinIspxclkByFreq 0x2C ///< Set HardMin by frequency for ISPXCLK
102-
#define PPSMC_MSG_PowerDownUmsch 0x2D ///< Power down VCN.UMSCH (aka VSCH) scheduler
103-
#define PPSMC_MSG_PowerUpUmsch 0x2E ///< Power up VCN.UMSCH (aka VSCH) scheduler
98+
#define PPSMC_MSG_PowerDownUmsch 0x2D ///< Power down VCN0.UMSCH (aka VSCH) scheduler
99+
#define PPSMC_MSG_PowerUpUmsch 0x2E ///< Power up VCN0.UMSCH (aka VSCH) scheduler
104100
#define PPSMC_Message_IspStutterOn_MmhubPgDis 0x2F ///< ISP StutterOn mmHub PgDis
105101
#define PPSMC_Message_IspStutterOff_MmhubPgEn 0x30 ///< ISP StufferOff mmHub PgEn
106102
#define PPSMC_MSG_PowerUpVpe 0x31 ///< Power up VPE
@@ -110,7 +106,9 @@
110106
#define PPSMC_MSG_DisableLSdma 0x35 ///< Disable LSDMA
111107
#define PPSMC_MSG_SetSoftMaxVpe 0x36 ///<
112108
#define PPSMC_MSG_SetSoftMinVpe 0x37 ///<
113-
#define PPSMC_Message_Count 0x38 ///< Total number of PPSMC messages
109+
#define PPSMC_MSG_AllocMALLCache 0x38 ///< Allocating MALL Cache
110+
#define PPSMC_MSG_ReleaseMALLCache 0x39 ///< Releasing MALL Cache
111+
#define PPSMC_Message_Count 0x3A ///< Total number of PPSMC messages
114112
/** @}*/
115113

116114
/**

‎drivers/gpu/drm/amd/pm/swsmu/inc/smu_v14_0.h‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -27,6 +27,7 @@
2727

2828
#define SMU14_DRIVER_IF_VERSION_INV 0xFFFFFFFF
2929
#define SMU14_DRIVER_IF_VERSION_SMU_V14_0_0 0x7
30+
#define SMU14_DRIVER_IF_VERSION_SMU_V14_0_1 0x6
3031
#define SMU14_DRIVER_IF_VERSION_SMU_V14_0_2 0x1
3132

3233
#define FEATURE_MASK(feature) (1ULL << feature)

‎drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -234,7 +234,7 @@ int smu_v14_0_check_fw_version(struct smu_context *smu)
234234
smu->smc_driver_if_version = SMU14_DRIVER_IF_VERSION_SMU_V14_0_0;
235235
break;
236236
case IP_VERSION(14, 0, 1):
237-
smu->smc_driver_if_version = SMU14_DRIVER_IF_VERSION_SMU_V14_0_0;
237+
smu->smc_driver_if_version = SMU14_DRIVER_IF_VERSION_SMU_V14_0_1;
238238
break;
239239

240240
default:

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