Skip to content

Commit c720a1f

Browse files
michalsimekmichalsimek
committed
arm64: zynqmp: Describe TI phy as ethernet-phy-id
TI DP83867 is using strapping based on MIO pins. Tristate setup can influence PHY address. That's why switch description with ethernet-phy-id compatible string which enable calling reset. PHY itself setups phy address after power up or reset. Phy reset is done via gpio. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/b49904649a363f40dc9c4d3fa275e42129562082.1684767562.git.michal.simek@amd.com
1 parent 4e4ddd3 commit c720a1f

6 files changed

Lines changed: 90 additions & 46 deletions

File tree

‎arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts‎

Lines changed: 15 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,8 @@
22
/*
33
* dts file for Xilinx ZynqMP ZCU102 RevA
44
*
5-
* (C) Copyright 2015 - 2021, Xilinx, Inc.
5+
* (C) Copyright 2015 - 2022, Xilinx, Inc.
6+
* (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
67
*
78
* Michal Simek <michal.simek@amd.com>
89
*/
@@ -200,13 +201,19 @@
200201
phy-mode = "rgmii-id";
201202
pinctrl-names = "default";
202203
pinctrl-0 = <&pinctrl_gem3_default>;
203-
phy0: ethernet-phy@21 {
204-
reg = <21>;
205-
ti,rx-internal-delay = <0x8>;
206-
ti,tx-internal-delay = <0xa>;
207-
ti,fifo-depth = <0x1>;
208-
ti,dp83867-rxctrl-strap-quirk;
209-
/* reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; */
204+
mdio: mdio {
205+
#address-cells = <1>;
206+
#size-cells = <0>;
207+
phy0: ethernet-phy@21 {
208+
#phy-cells = <1>;
209+
compatible = "ethernet-phy-id2000.a231";
210+
reg = <21>;
211+
ti,rx-internal-delay = <0x8>;
212+
ti,tx-internal-delay = <0xa>;
213+
ti,fifo-depth = <0x1>;
214+
ti,dp83867-rxctrl-strap-quirk;
215+
reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>;
216+
};
210217
};
211218
};
212219

‎arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revB.dts‎

Lines changed: 15 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,8 @@
22
/*
33
* dts file for Xilinx ZynqMP ZCU102 RevB
44
*
5-
* (C) Copyright 2016 - 2021, Xilinx, Inc.
5+
* (C) Copyright 2016 - 2022, Xilinx, Inc.
6+
* (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
67
*
78
* Michal Simek <michal.simek@amd.com>
89
*/
@@ -16,16 +17,20 @@
1617

1718
&gem3 {
1819
phy-handle = <&phyc>;
19-
phyc: ethernet-phy@c {
20-
reg = <0xc>;
21-
ti,rx-internal-delay = <0x8>;
22-
ti,tx-internal-delay = <0xa>;
23-
ti,fifo-depth = <0x1>;
24-
ti,dp83867-rxctrl-strap-quirk;
25-
/* reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; */
20+
mdio: mdio {
21+
phyc: ethernet-phy@c {
22+
#phy-cells = <0x1>;
23+
compatible = "ethernet-phy-id2000.a231";
24+
reg = <0xc>;
25+
ti,rx-internal-delay = <0x8>;
26+
ti,tx-internal-delay = <0xa>;
27+
ti,fifo-depth = <0x1>;
28+
ti,dp83867-rxctrl-strap-quirk;
29+
reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>;
30+
};
31+
/* Cleanup from RevA */
32+
/delete-node/ ethernet-phy@21;
2633
};
27-
/* Cleanup from RevA */
28-
/delete-node/ ethernet-phy@21;
2934
};
3035

3136
/* Fix collision with u61 */

‎arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts‎

Lines changed: 15 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,8 @@
22
/*
33
* dts file for Xilinx ZynqMP ZCU104
44
*
5-
* (C) Copyright 2017 - 2021, Xilinx, Inc.
5+
* (C) Copyright 2017 - 2022, Xilinx, Inc.
6+
* (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
67
*
78
* Michal Simek <michal.simek@amd.com>
89
*/
@@ -109,12 +110,19 @@
109110
phy-mode = "rgmii-id";
110111
pinctrl-names = "default";
111112
pinctrl-0 = <&pinctrl_gem3_default>;
112-
phy0: ethernet-phy@c {
113-
reg = <0xc>;
114-
ti,rx-internal-delay = <0x8>;
115-
ti,tx-internal-delay = <0xa>;
116-
ti,fifo-depth = <0x1>;
117-
ti,dp83867-rxctrl-strap-quirk;
113+
mdio: mdio {
114+
#address-cells = <1>;
115+
#size-cells = <0>;
116+
phy0: ethernet-phy@c {
117+
#phy-cells = <1>;
118+
compatible = "ethernet-phy-id2000.a231";
119+
reg = <0xc>;
120+
ti,rx-internal-delay = <0x8>;
121+
ti,tx-internal-delay = <0xa>;
122+
ti,fifo-depth = <0x1>;
123+
ti,dp83867-rxctrl-strap-quirk;
124+
reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>;
125+
};
118126
};
119127
};
120128

‎arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts‎

Lines changed: 15 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,8 @@
22
/*
33
* dts file for Xilinx ZynqMP ZCU104
44
*
5-
* (C) Copyright 2017 - 2021, Xilinx, Inc.
5+
* (C) Copyright 2017 - 2022, Xilinx, Inc.
6+
* (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
67
*
78
* Michal Simek <michal.simek@amd.com>
89
*/
@@ -114,12 +115,19 @@
114115
phy-mode = "rgmii-id";
115116
pinctrl-names = "default";
116117
pinctrl-0 = <&pinctrl_gem3_default>;
117-
phy0: ethernet-phy@c {
118-
reg = <0xc>;
119-
ti,rx-internal-delay = <0x8>;
120-
ti,tx-internal-delay = <0xa>;
121-
ti,fifo-depth = <0x1>;
122-
ti,dp83867-rxctrl-strap-quirk;
118+
mdio: mdio {
119+
#address-cells = <1>;
120+
#size-cells = <0>;
121+
phy0: ethernet-phy@c {
122+
#phy-cells = <1>;
123+
compatible = "ethernet-phy-id2000.a231";
124+
reg = <0xc>;
125+
ti,rx-internal-delay = <0x8>;
126+
ti,tx-internal-delay = <0xa>;
127+
ti,fifo-depth = <0x1>;
128+
ti,dp83867-rxctrl-strap-quirk;
129+
reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>;
130+
};
123131
};
124132
};
125133

‎arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts‎

Lines changed: 15 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,8 @@
22
/*
33
* dts file for Xilinx ZynqMP ZCU106
44
*
5-
* (C) Copyright 2016 - 2021, Xilinx, Inc.
5+
* (C) Copyright 2016 - 2022, Xilinx, Inc.
6+
* (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
67
*
78
* Michal Simek <michal.simek@amd.com>
89
*/
@@ -212,12 +213,19 @@
212213
phy-mode = "rgmii-id";
213214
pinctrl-names = "default";
214215
pinctrl-0 = <&pinctrl_gem3_default>;
215-
phy0: ethernet-phy@c {
216-
reg = <0xc>;
217-
ti,rx-internal-delay = <0x8>;
218-
ti,tx-internal-delay = <0xa>;
219-
ti,fifo-depth = <0x1>;
220-
ti,dp83867-rxctrl-strap-quirk;
216+
mdio: mdio {
217+
#address-cells = <1>;
218+
#size-cells = <0>;
219+
phy0: ethernet-phy@c {
220+
#phy-cells = <1>;
221+
reg = <0xc>;
222+
compatible = "ethernet-phy-id2000.a231";
223+
ti,rx-internal-delay = <0x8>;
224+
ti,tx-internal-delay = <0xa>;
225+
ti,fifo-depth = <0x1>;
226+
ti,dp83867-rxctrl-strap-quirk;
227+
reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>;
228+
};
221229
};
222230
};
223231

‎arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts‎

Lines changed: 15 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,8 @@
22
/*
33
* dts file for Xilinx ZynqMP ZCU111
44
*
5-
* (C) Copyright 2017 - 2021, Xilinx, Inc.
5+
* (C) Copyright 2017 - 2022, Xilinx, Inc.
6+
* (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
67
*
78
* Michal Simek <michal.simek@amd.com>
89
*/
@@ -172,12 +173,19 @@
172173
phy-mode = "rgmii-id";
173174
pinctrl-names = "default";
174175
pinctrl-0 = <&pinctrl_gem3_default>;
175-
phy0: ethernet-phy@c {
176-
reg = <0xc>;
177-
ti,rx-internal-delay = <0x8>;
178-
ti,tx-internal-delay = <0xa>;
179-
ti,fifo-depth = <0x1>;
180-
ti,dp83867-rxctrl-strap-quirk;
176+
mdio: mdio {
177+
#address-cells = <1>;
178+
#size-cells = <0>;
179+
phy0: ethernet-phy@c {
180+
#phy-cells = <1>;
181+
compatible = "ethernet-phy-id2000.a231";
182+
reg = <0xc>;
183+
ti,rx-internal-delay = <0x8>;
184+
ti,tx-internal-delay = <0xa>;
185+
ti,fifo-depth = <0x1>;
186+
ti,dp83867-rxctrl-strap-quirk;
187+
reset-gpios = <&tca6416_u22 6 GPIO_ACTIVE_LOW>;
188+
};
181189
};
182190
};
183191

0 commit comments

Comments
 (0)