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thierryredingthierryreding
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arm64: tegra: Enable SMMU support on Tegra194
Add the device tree node for the dual-SMMU found on Tegra194 and hook up peripherals such as host1x, BPMP, HDA, SDMMC, EQOS and VIC. Signed-off-by: Thierry Reding <treding@nvidia.com>
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‎arch/arm64/boot/dts/nvidia/tegra194.dtsi‎

Lines changed: 86 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -62,6 +62,7 @@
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interconnects = <&mc TEGRA194_MEMORY_CLIENT_EQOSR &emc>,
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<&mc TEGRA194_MEMORY_CLIENT_EQOSW &emc>;
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interconnect-names = "dma-mem", "write";
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iommus = <&smmu TEGRA194_SID_EQOS>;
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status = "disabled";
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snps,write-requests = <1>;
@@ -733,6 +734,7 @@
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interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRA &emc>,
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<&mc TEGRA194_MEMORY_CLIENT_SDMMCWA &emc>;
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interconnect-names = "dma-mem", "write";
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iommus = <&smmu TEGRA194_SID_SDMMC1>;
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nvidia,pad-autocal-pull-up-offset-3v3-timeout =
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<0x07>;
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nvidia,pad-autocal-pull-down-offset-3v3-timeout =
@@ -759,6 +761,7 @@
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interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCR &emc>,
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<&mc TEGRA194_MEMORY_CLIENT_SDMMCW &emc>;
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interconnect-names = "dma-mem", "write";
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iommus = <&smmu TEGRA194_SID_SDMMC3>;
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nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>;
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nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>;
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nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
@@ -790,6 +793,7 @@
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interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRAB &emc>,
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<&mc TEGRA194_MEMORY_CLIENT_SDMMCWAB &emc>;
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interconnect-names = "dma-mem", "write";
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iommus = <&smmu TEGRA194_SID_SDMMC4>;
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nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>;
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nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>;
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nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>;
@@ -821,6 +825,7 @@
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interconnects = <&mc TEGRA194_MEMORY_CLIENT_HDAR &emc>,
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<&mc TEGRA194_MEMORY_CLIENT_HDAW &emc>;
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interconnect-names = "dma-mem", "write";
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iommus = <&smmu TEGRA194_SID_HDA>;
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status = "disabled";
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};
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@@ -1300,6 +1305,84 @@
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interrupt-controller;
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};
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smmu: iommu@12000000 {
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compatible = "nvidia,tegra194-smmu", "nvidia,smmu-500";
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reg = <0x12000000 0x800000>,
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<0x11000000 0x800000>;
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interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
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stream-match-mask = <0x7f80>;
1379+
#global-interrupts = <2>;
1380+
#iommu-cells = <1>;
1381+
1382+
nvidia,memory-controller = <&mc>;
1383+
status = "okay";
1384+
};
1385+
13031386
host1x@13e00000 {
13041387
compatible = "nvidia,tegra194-host1x";
13051388
reg = <0x13e00000 0x10000>,
@@ -1319,6 +1402,7 @@
13191402
ranges = <0x15000000 0x15000000 0x01000000>;
13201403
interconnects = <&mc TEGRA194_MEMORY_CLIENT_HOST1XDMAR &emc>;
13211404
interconnect-names = "dma-mem";
1405+
iommus = <&smmu TEGRA194_SID_HOST1X>;
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13231407
display-hub@15200000 {
13241408
compatible = "nvidia,tegra194-display";
@@ -1430,6 +1514,7 @@
14301514
interconnects = <&mc TEGRA194_MEMORY_CLIENT_VICSRD &emc>,
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<&mc TEGRA194_MEMORY_CLIENT_VICSWR &emc>;
14321516
interconnect-names = "dma-mem", "write";
1517+
iommus = <&smmu TEGRA194_SID_VIC>;
14331518
};
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14351520
dpaux0: dpaux@155c0000 {
@@ -2136,6 +2221,7 @@
21362221
<&mc TEGRA194_MEMORY_CLIENT_BPMPDMAR &emc>,
21372222
<&mc TEGRA194_MEMORY_CLIENT_BPMPDMAW &emc>;
21382223
interconnect-names = "read", "write", "dma-mem", "dma-write";
2224+
iommus = <&smmu TEGRA194_SID_BPMP>;
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21402226
bpmp_i2c: i2c {
21412227
compatible = "nvidia,tegra186-bpmp-i2c";

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