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clk: amlogic: add video-related clocks for S4 SoC
Add video encoder, demodulator and CVBS clocks. Signed-off-by: Chuan Liu <chuan.liu@amlogic.com> Link: https://lore.kernel.org/r/20250919-add_video_clk-v6-2-fe223161fb3f@amlogic.com Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
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‎drivers/clk/meson/s4-peripherals.c‎

Lines changed: 202 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -44,6 +44,7 @@
4444
#define CLKCTRL_VDIN_MEAS_CLK_CTRL 0x0f8
4545
#define CLKCTRL_VAPBCLK_CTRL 0x0fc
4646
#define CLKCTRL_HDCP22_CTRL 0x100
47+
#define CLKCTRL_CDAC_CLK_CTRL 0x108
4748
#define CLKCTRL_VDEC_CLK_CTRL 0x140
4849
#define CLKCTRL_VDEC2_CLK_CTRL 0x144
4950
#define CLKCTRL_VDEC3_CLK_CTRL 0x148
@@ -1126,6 +1127,21 @@ static struct clk_regmap s4_cts_encp_sel = {
11261127
},
11271128
};
11281129

1130+
static struct clk_regmap s4_cts_encl_sel = {
1131+
.data = &(struct clk_regmap_mux_data){
1132+
.offset = CLKCTRL_VIID_CLK_DIV,
1133+
.mask = 0xf,
1134+
.shift = 12,
1135+
.table = s4_cts_parents_val_table,
1136+
},
1137+
.hw.init = &(struct clk_init_data){
1138+
.name = "cts_encl_sel",
1139+
.ops = &clk_regmap_mux_ops,
1140+
.parent_hws = s4_cts_parents,
1141+
.num_parents = ARRAY_SIZE(s4_cts_parents),
1142+
},
1143+
};
1144+
11291145
static struct clk_regmap s4_cts_vdac_sel = {
11301146
.data = &(struct clk_regmap_mux_data){
11311147
.offset = CLKCTRL_VIID_CLK_DIV,
@@ -1205,6 +1221,22 @@ static struct clk_regmap s4_cts_encp = {
12051221
},
12061222
};
12071223

1224+
static struct clk_regmap s4_cts_encl = {
1225+
.data = &(struct clk_regmap_gate_data){
1226+
.offset = CLKCTRL_VID_CLK_CTRL2,
1227+
.bit_idx = 3,
1228+
},
1229+
.hw.init = &(struct clk_init_data) {
1230+
.name = "cts_encl",
1231+
.ops = &clk_regmap_gate_ops,
1232+
.parent_hws = (const struct clk_hw *[]) {
1233+
&s4_cts_encl_sel.hw
1234+
},
1235+
.num_parents = 1,
1236+
.flags = CLK_SET_RATE_PARENT,
1237+
},
1238+
};
1239+
12081240
static struct clk_regmap s4_cts_vdac = {
12091241
.data = &(struct clk_regmap_gate_data){
12101242
.offset = CLKCTRL_VID_CLK_CTRL2,
@@ -2735,6 +2767,165 @@ static struct clk_regmap s4_gen_clk = {
27352767
},
27362768
};
27372769

2770+
/* CVBS DAC */
2771+
static struct clk_regmap s4_cdac_sel = {
2772+
.data = &(struct clk_regmap_mux_data) {
2773+
.offset = CLKCTRL_CDAC_CLK_CTRL,
2774+
.mask = 0x3,
2775+
.shift = 16,
2776+
},
2777+
.hw.init = &(struct clk_init_data){
2778+
.name = "cdac_sel",
2779+
.ops = &clk_regmap_mux_ops,
2780+
.parent_data = (const struct clk_parent_data []) {
2781+
{ .fw_name = "xtal", },
2782+
{ .fw_name = "fclk_div5" },
2783+
},
2784+
.num_parents = 2,
2785+
},
2786+
};
2787+
2788+
static struct clk_regmap s4_cdac_div = {
2789+
.data = &(struct clk_regmap_div_data) {
2790+
.offset = CLKCTRL_CDAC_CLK_CTRL,
2791+
.shift = 0,
2792+
.width = 16,
2793+
},
2794+
.hw.init = &(struct clk_init_data){
2795+
.name = "cdac_div",
2796+
.ops = &clk_regmap_divider_ops,
2797+
.parent_hws = (const struct clk_hw *[]) {
2798+
&s4_cdac_sel.hw
2799+
},
2800+
.num_parents = 1,
2801+
.flags = CLK_SET_RATE_PARENT,
2802+
},
2803+
};
2804+
2805+
static struct clk_regmap s4_cdac = {
2806+
.data = &(struct clk_regmap_gate_data) {
2807+
.offset = CLKCTRL_CDAC_CLK_CTRL,
2808+
.bit_idx = 20,
2809+
},
2810+
.hw.init = &(struct clk_init_data){
2811+
.name = "cdac",
2812+
.ops = &clk_regmap_gate_ops,
2813+
.parent_hws = (const struct clk_hw *[]) {
2814+
&s4_cdac_div.hw
2815+
},
2816+
.num_parents = 1,
2817+
.flags = CLK_SET_RATE_PARENT,
2818+
},
2819+
};
2820+
2821+
static struct clk_regmap s4_demod_core_sel = {
2822+
.data = &(struct clk_regmap_mux_data) {
2823+
.offset = CLKCTRL_DEMOD_CLK_CTRL,
2824+
.mask = 0x3,
2825+
.shift = 9,
2826+
},
2827+
.hw.init = &(struct clk_init_data){
2828+
.name = "demod_core_sel",
2829+
.ops = &clk_regmap_mux_ops,
2830+
.parent_data = (const struct clk_parent_data []) {
2831+
{ .fw_name = "xtal" },
2832+
{ .fw_name = "fclk_div7" },
2833+
{ .fw_name = "fclk_div4" }
2834+
},
2835+
.num_parents = 3,
2836+
},
2837+
};
2838+
2839+
static struct clk_regmap s4_demod_core_div = {
2840+
.data = &(struct clk_regmap_div_data) {
2841+
.offset = CLKCTRL_DEMOD_CLK_CTRL,
2842+
.shift = 0,
2843+
.width = 7,
2844+
},
2845+
.hw.init = &(struct clk_init_data){
2846+
.name = "demod_core_div",
2847+
.ops = &clk_regmap_divider_ops,
2848+
.parent_hws = (const struct clk_hw *[]) {
2849+
&s4_demod_core_sel.hw
2850+
},
2851+
.num_parents = 1,
2852+
.flags = CLK_SET_RATE_PARENT,
2853+
},
2854+
};
2855+
2856+
static struct clk_regmap s4_demod_core = {
2857+
.data = &(struct clk_regmap_gate_data) {
2858+
.offset = CLKCTRL_DEMOD_CLK_CTRL,
2859+
.bit_idx = 8
2860+
},
2861+
.hw.init = &(struct clk_init_data){
2862+
.name = "demod_core",
2863+
.ops = &clk_regmap_gate_ops,
2864+
.parent_hws = (const struct clk_hw *[]) {
2865+
&s4_demod_core_div.hw
2866+
},
2867+
.num_parents = 1,
2868+
.flags = CLK_SET_RATE_PARENT,
2869+
},
2870+
};
2871+
2872+
/* CVBS ADC */
2873+
static struct clk_regmap s4_adc_extclk_in_sel = {
2874+
.data = &(struct clk_regmap_mux_data) {
2875+
.offset = CLKCTRL_DEMOD_CLK_CTRL,
2876+
.mask = 0x7,
2877+
.shift = 25,
2878+
},
2879+
.hw.init = &(struct clk_init_data){
2880+
.name = "adc_extclk_in_sel",
2881+
.ops = &clk_regmap_mux_ops,
2882+
.parent_data = (const struct clk_parent_data []) {
2883+
{ .fw_name = "xtal" },
2884+
{ .fw_name = "fclk_div4" },
2885+
{ .fw_name = "fclk_div3" },
2886+
{ .fw_name = "fclk_div5" },
2887+
{ .fw_name = "fclk_div7" },
2888+
{ .fw_name = "mpll2" },
2889+
{ .fw_name = "gp0_pll" },
2890+
{ .fw_name = "hifi_pll" }
2891+
},
2892+
.num_parents = 8,
2893+
},
2894+
};
2895+
2896+
static struct clk_regmap s4_adc_extclk_in_div = {
2897+
.data = &(struct clk_regmap_div_data) {
2898+
.offset = CLKCTRL_DEMOD_CLK_CTRL,
2899+
.shift = 16,
2900+
.width = 7,
2901+
},
2902+
.hw.init = &(struct clk_init_data){
2903+
.name = "adc_extclk_in_div",
2904+
.ops = &clk_regmap_divider_ops,
2905+
.parent_hws = (const struct clk_hw *[]) {
2906+
&s4_adc_extclk_in_sel.hw
2907+
},
2908+
.num_parents = 1,
2909+
.flags = CLK_SET_RATE_PARENT,
2910+
},
2911+
};
2912+
2913+
static struct clk_regmap s4_adc_extclk_in = {
2914+
.data = &(struct clk_regmap_gate_data) {
2915+
.offset = CLKCTRL_DEMOD_CLK_CTRL,
2916+
.bit_idx = 24
2917+
},
2918+
.hw.init = &(struct clk_init_data){
2919+
.name = "adc_extclk_in",
2920+
.ops = &clk_regmap_gate_ops,
2921+
.parent_hws = (const struct clk_hw *[]) {
2922+
&s4_adc_extclk_in_div.hw
2923+
},
2924+
.num_parents = 1,
2925+
.flags = CLK_SET_RATE_PARENT,
2926+
},
2927+
};
2928+
27382929
static const struct clk_parent_data s4_pclk_parents = { .hw = &s4_sys_clk.hw };
27392930

27402931
#define S4_PCLK(_name, _reg, _bit, _flags) \
@@ -3028,6 +3219,17 @@ static struct clk_hw *s4_peripherals_hw_clks[] = {
30283219
[CLKID_HDCP22_SKPCLK_SEL] = &s4_hdcp22_skpclk_sel.hw,
30293220
[CLKID_HDCP22_SKPCLK_DIV] = &s4_hdcp22_skpclk_div.hw,
30303221
[CLKID_HDCP22_SKPCLK] = &s4_hdcp22_skpclk.hw,
3222+
[CLKID_CTS_ENCL_SEL] = &s4_cts_encl_sel.hw,
3223+
[CLKID_CTS_ENCL] = &s4_cts_encl.hw,
3224+
[CLKID_CDAC_SEL] = &s4_cdac_sel.hw,
3225+
[CLKID_CDAC_DIV] = &s4_cdac_div.hw,
3226+
[CLKID_CDAC] = &s4_cdac.hw,
3227+
[CLKID_DEMOD_CORE_SEL] = &s4_demod_core_sel.hw,
3228+
[CLKID_DEMOD_CORE_DIV] = &s4_demod_core_div.hw,
3229+
[CLKID_DEMOD_CORE] = &s4_demod_core.hw,
3230+
[CLKID_ADC_EXTCLK_IN_SEL] = &s4_adc_extclk_in_sel.hw,
3231+
[CLKID_ADC_EXTCLK_IN_DIV] = &s4_adc_extclk_in_div.hw,
3232+
[CLKID_ADC_EXTCLK_IN] = &s4_adc_extclk_in.hw,
30313233
};
30323234

30333235
static const struct meson_clkc_data s4_peripherals_clkc_data = {

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