Skip to content

Commit c793011

Browse files
torvaldstorvalds
committed
Merge tag 'pinctrl-v5.15-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control updates from Linus Walleij: "This is the bulk of pin control changes for the v5.15 kernel cycle, no core changes at all this time, just driver work! New drivers: - New subdriver for Intel Keem Bay (an ARM-based SoC) - New subdriver for Qualcomm MDM9607 and SM6115 - New subdriver for ST Microelectronics STM32MP135 - New subdriver for Freescale i.MX8ULP ("Ultra Low Power") - New subdriver for Ingenic X2100 - Support for Qualcomm PMC8180, PMC8180C, SA8155p-adp PMIC GPIO - Support Samsung Exynos850 - Support Renesas RZ/G2L Enhancements: - A major refactoring of the Rockchip driver, breaking part of it out to a separate GPIO driver in drivers/gpio - Pin bias support on Renesas r8a77995 - Add SCI pins support to Ingenic JZ4755 and JZ4760 - Mediatek device tree bindings converted to YAML" * tag 'pinctrl-v5.15-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (53 commits) pinctrl: renesas: Add RZ/G2L pin and gpio controller driver pinctrl: samsung: Add Exynos850 SoC specific data dt-bindings: pinctrl: samsung: Add Exynos850 doc MAINTAINERS: Add maintainers for amd-pinctrl driver pinctrl: Add Intel Keem Bay pinctrl driver dt-bindings: pinctrl: Add bindings for Intel Keembay pinctrl driver pinctrl: zynqmp: Drop pinctrl_unregister for devm_ registered device dt-bindings: pinctrl: qcom-pmic-gpio: Remove the interrupts property dt-bindings: pinctrl: qcom-pmic-gpio: Convert qcom pmic gpio bindings to YAML dt-bindings: pinctrl: mt8195: Use real world values for drive-strength arguments dt-bindings: mediatek: convert pinctrl to yaml arm: dts: mt8183: Move pinfunc to include/dt-bindings/pinctrl arm: dts: mt8135: Move pinfunc to include/dt-bindings/pinctrl pinctrl: ingenic: Add .max_register in regmap_config pinctrl: ingenic: Fix bias config for X2000(E) pinctrl: ingenic: Fix incorrect pull up/down info pinctrl: Ingenic: Add pinctrl driver for X2100. dt-bindings: pinctrl: Add bindings for Ingenic X2100. pinctrl: Ingenic: Add SSI pins support for JZ4755 and JZ4760. pinctrl: Ingenic: Improve the code. ...
2 parents 75d6e7d + 0485335 commit c793011

67 files changed

Lines changed: 10134 additions & 1440 deletions

Some content is hidden

Large Commits have some content hidden by default. Use the searchbox below for content that may be hidden.

‎Documentation/devicetree/bindings/pinctrl/fsl,imx8ulp-pinctrl.yaml‎

Lines changed: 79 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,79 @@
1+
# SPDX-License-Identifier: GPL-2.0
2+
%YAML 1.2
3+
---
4+
$id: http://devicetree.org/schemas/pinctrl/fsl,imx8ulp-pinctrl.yaml#
5+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6+
7+
title: Freescale IMX8ULP IOMUX Controller
8+
9+
maintainers:
10+
- Jacky Bai <ping.bai@nxp.com>
11+
12+
description:
13+
Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory
14+
for common binding part and usage.
15+
16+
properties:
17+
compatible:
18+
const: fsl,imx8ulp-iomuxc1
19+
20+
reg:
21+
maxItems: 1
22+
23+
# Client device subnode's properties
24+
patternProperties:
25+
'grp$':
26+
type: object
27+
description:
28+
Pinctrl node's client devices use subnodes for desired pin configuration.
29+
Client device subnodes use below standard properties.
30+
31+
properties:
32+
fsl,pins:
33+
description:
34+
each entry consists of 5 integers and represents the mux and config
35+
setting for one pin. The first 4 integers <mux_config_reg input_reg
36+
mux_mode input_val> are specified using a PIN_FUNC_ID macro, which can
37+
be found in <arch/arm64/boot/dts/freescale/imx8ulp-pinfunc.h>. The last
38+
integer CONFIG is the pad setting value like pull-up on this pin. Please
39+
refer to i.MX8ULP Reference Manual for detailed CONFIG settings.
40+
$ref: /schemas/types.yaml#/definitions/uint32-matrix
41+
items:
42+
items:
43+
- description: |
44+
"mux_config_reg" indicates the offset of mux register.
45+
- description: |
46+
"input_reg" indicates the offset of select input register.
47+
- description: |
48+
"mux_mode" indicates the mux value to be applied.
49+
- description: |
50+
"input_val" indicates the select input value to be applied.
51+
- description: |
52+
"pad_setting" indicates the pad configuration value to be applied.
53+
54+
required:
55+
- fsl,pins
56+
57+
additionalProperties: false
58+
59+
required:
60+
- compatible
61+
- reg
62+
63+
additionalProperties: false
64+
65+
examples:
66+
# Pinmux controller node
67+
- |
68+
iomuxc: pinctrl@298c0000 {
69+
compatible = "fsl,imx8ulp-iomuxc1";
70+
reg = <0x298c0000 0x10000>;
71+
72+
pinctrl_lpuart5: lpuart5grp {
73+
fsl,pins =
74+
<0x0138 0x08F0 0x4 0x3 0x3>,
75+
<0x013C 0x08EC 0x4 0x3 0x3>;
76+
};
77+
};
78+
79+
...

‎Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.yaml‎

Lines changed: 6 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -19,10 +19,10 @@ description: >
1919
pin within that GPIO port. For example PA0 is the first pin in GPIO port A,
2020
and PB31 is the last pin in GPIO port B. The JZ4730, the JZ4740, the JZ4725B,
2121
the X1000 and the X1830 contains 4 GPIO ports, PA to PD, for a total of 128
22-
pins. The X2000 contains 5 GPIO ports, PA to PE, for a total of 160 pins.
23-
The JZ4750, the JZ4755 the JZ4760, the JZ4770 and the JZ4780 contains 6 GPIO
24-
ports, PA to PF, for a total of 192 pins. The JZ4775 contains 7 GPIO ports,
25-
PA to PG, for a total of 224 pins.
22+
pins. The X2000 and the X2100 contains 5 GPIO ports, PA to PE, for a total of
23+
160 pins. The JZ4750, the JZ4755 the JZ4760, the JZ4770 and the JZ4780 contains
24+
6 GPIO ports, PA to PF, for a total of 192 pins. The JZ4775 contains 7 GPIO
25+
ports, PA to PG, for a total of 224 pins.
2626
2727
maintainers:
2828
- Paul Cercueil <paul@crapouillou.net>
@@ -47,6 +47,7 @@ properties:
4747
- ingenic,x1500-pinctrl
4848
- ingenic,x1830-pinctrl
4949
- ingenic,x2000-pinctrl
50+
- ingenic,x2100-pinctrl
5051
- items:
5152
- const: ingenic,jz4760b-pinctrl
5253
- const: ingenic,jz4760-pinctrl
@@ -85,6 +86,7 @@ patternProperties:
8586
- ingenic,x1500-gpio
8687
- ingenic,x1830-gpio
8788
- ingenic,x2000-gpio
89+
- ingenic,x2100-gpio
8890

8991
reg:
9092
items:

‎Documentation/devicetree/bindings/pinctrl/intel,pinctrl-keembay.yaml‎

Lines changed: 135 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,135 @@
1+
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2+
%YAML 1.2
3+
---
4+
$id: http://devicetree.org/schemas/pinctrl/intel,pinctrl-keembay.yaml#
5+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6+
7+
title: Intel Keem Bay pin controller Device Tree Bindings
8+
9+
maintainers:
10+
- Lakshmi Sowjanya D <lakshmi.sowjanya.d@intel.com>
11+
12+
description: |
13+
Intel Keem Bay SoC integrates a pin controller which enables control
14+
of pin directions, input/output values and configuration
15+
for a total of 80 pins.
16+
17+
properties:
18+
compatible:
19+
const: intel,keembay-pinctrl
20+
21+
reg:
22+
maxItems: 2
23+
24+
gpio-controller: true
25+
26+
'#gpio-cells':
27+
const: 2
28+
29+
ngpios:
30+
description: The number of GPIOs exposed.
31+
const: 80
32+
33+
interrupts:
34+
description:
35+
Specifies the interrupt lines to be used by the controller.
36+
Each interrupt line is shared by upto 4 GPIO lines.
37+
maxItems: 8
38+
39+
interrupt-controller: true
40+
41+
'#interrupt-cells':
42+
const: 2
43+
44+
patternProperties:
45+
'^gpio@[0-9a-f]*$':
46+
type: object
47+
48+
description:
49+
Child nodes can be specified to contain pin configuration information,
50+
which can then be utilized by pinctrl client devices.
51+
The following properties are supported.
52+
53+
properties:
54+
pins:
55+
description: |
56+
The name(s) of the pins to be configured in the child node.
57+
Supported pin names are "GPIO0" up to "GPIO79".
58+
59+
bias-disable: true
60+
61+
bias-pull-down: true
62+
63+
bias-pull-up: true
64+
65+
drive-strength:
66+
description: IO pads drive strength in milli Ampere.
67+
enum: [2, 4, 8, 12]
68+
69+
bias-bus-hold:
70+
type: boolean
71+
72+
input-schmitt-enable:
73+
type: boolean
74+
75+
slew-rate:
76+
description: GPIO slew rate control.
77+
0 - Fast(~100MHz)
78+
1 - Slow(~50MHz)
79+
enum: [0, 1]
80+
81+
additionalProperties: false
82+
83+
required:
84+
- compatible
85+
- reg
86+
- gpio-controller
87+
- ngpios
88+
- '#gpio-cells'
89+
- interrupts
90+
- interrupt-controller
91+
- '#interrupt-cells'
92+
93+
examples:
94+
- |
95+
#include <dt-bindings/interrupt-controller/arm-gic.h>
96+
#include <dt-bindings/interrupt-controller/irq.h>
97+
// Example 1
98+
gpio@0 {
99+
compatible = "intel,keembay-pinctrl";
100+
reg = <0x600b0000 0x88>,
101+
<0x600b0190 0x1ac>;
102+
gpio-controller;
103+
ngpios = <0x50>;
104+
#gpio-cells = <0x2>;
105+
interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
106+
<GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
107+
<GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
108+
<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
109+
<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
110+
<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
111+
<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
112+
<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
113+
interrupt-controller;
114+
#interrupt-cells = <2>;
115+
};
116+
117+
// Example 2
118+
gpio@1 {
119+
compatible = "intel,keembay-pinctrl";
120+
reg = <0x600c0000 0x88>,
121+
<0x600c0190 0x1ac>;
122+
gpio-controller;
123+
ngpios = <0x50>;
124+
#gpio-cells = <0x2>;
125+
interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
126+
<GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
127+
<GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
128+
<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
129+
<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
130+
<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
131+
<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
132+
<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
133+
interrupt-controller;
134+
#interrupt-cells = <2>;
135+
};

‎Documentation/devicetree/bindings/pinctrl/marvell,armada-37xx-pinctrl.txt‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -43,19 +43,19 @@ group emmc_nb
4343

4444
group pwm0
4545
- pin 11 (GPIO1-11)
46-
- functions pwm, gpio
46+
- functions pwm, led, gpio
4747

4848
group pwm1
4949
- pin 12
50-
- functions pwm, gpio
50+
- functions pwm, led, gpio
5151

5252
group pwm2
5353
- pin 13
54-
- functions pwm, gpio
54+
- functions pwm, led, gpio
5555

5656
group pwm3
5757
- pin 14
58-
- functions pwm, gpio
58+
- functions pwm, led, gpio
5959

6060
group pmic1
6161
- pin 7

0 commit comments

Comments
 (0)