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Dapeng MiPeter Zijlstra
Dapeng Mi
authored and
Peter Zijlstra
committed
perf/x86/intel: Add core PMU support for Novalake
This patch enables core PMU support for Novalake, covering both P-core and E-core. It includes Arctic Wolf-specific counters and PEBS constraints, and the model-specific OMR extra registers table. Since Coyote Cove shares the same PMU capabilities as Panther Cove, the existing Panther Cove PMU enabling functions are reused for Coyote Cove. For detailed information about counter constraints, please refer to section 16.3 "COUNTER RESTRICTIONS" in the ISE documentation. Signed-off-by: Dapeng Mi <dapeng1.mi@linux.intel.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Link: https://patch.msgid.link/20260114011750.350569-6-dapeng1.mi@linux.intel.com
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‎arch/x86/events/intel/core.c‎

Lines changed: 99 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -232,6 +232,29 @@ static struct event_constraint intel_skt_event_constraints[] __read_mostly = {
232232
EVENT_CONSTRAINT_END
233233
};
234234

235+
static struct event_constraint intel_arw_event_constraints[] __read_mostly = {
236+
FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
237+
FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
238+
FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF */
239+
FIXED_EVENT_CONSTRAINT(0x013c, 2), /* CPU_CLK_UNHALTED.REF_TSC_P */
240+
FIXED_EVENT_CONSTRAINT(0x0073, 4), /* TOPDOWN_BAD_SPECULATION.ALL */
241+
FIXED_EVENT_CONSTRAINT(0x019c, 5), /* TOPDOWN_FE_BOUND.ALL */
242+
FIXED_EVENT_CONSTRAINT(0x02c2, 6), /* TOPDOWN_RETIRING.ALL */
243+
INTEL_UEVENT_CONSTRAINT(0x01b7, 0x1),
244+
INTEL_UEVENT_CONSTRAINT(0x02b7, 0x2),
245+
INTEL_UEVENT_CONSTRAINT(0x04b7, 0x4),
246+
INTEL_UEVENT_CONSTRAINT(0x08b7, 0x8),
247+
INTEL_UEVENT_CONSTRAINT(0x01d4, 0x1),
248+
INTEL_UEVENT_CONSTRAINT(0x02d4, 0x2),
249+
INTEL_UEVENT_CONSTRAINT(0x04d4, 0x4),
250+
INTEL_UEVENT_CONSTRAINT(0x08d4, 0x8),
251+
INTEL_UEVENT_CONSTRAINT(0x0175, 0x1),
252+
INTEL_UEVENT_CONSTRAINT(0x0275, 0x2),
253+
INTEL_UEVENT_CONSTRAINT(0x21d3, 0x1),
254+
INTEL_UEVENT_CONSTRAINT(0x22d3, 0x1),
255+
EVENT_CONSTRAINT_END
256+
};
257+
235258
static struct event_constraint intel_skl_event_constraints[] = {
236259
FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
237260
FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
@@ -2319,6 +2342,26 @@ static __initconst const u64 tnt_hw_cache_extra_regs
23192342
},
23202343
};
23212344

2345+
static __initconst const u64 arw_hw_cache_extra_regs
2346+
[PERF_COUNT_HW_CACHE_MAX]
2347+
[PERF_COUNT_HW_CACHE_OP_MAX]
2348+
[PERF_COUNT_HW_CACHE_RESULT_MAX] = {
2349+
[C(LL)] = {
2350+
[C(OP_READ)] = {
2351+
[C(RESULT_ACCESS)] = 0x4000000000000001,
2352+
[C(RESULT_MISS)] = 0xFFFFF000000001,
2353+
},
2354+
[C(OP_WRITE)] = {
2355+
[C(RESULT_ACCESS)] = 0x4000000000000002,
2356+
[C(RESULT_MISS)] = 0xFFFFF000000002,
2357+
},
2358+
[C(OP_PREFETCH)] = {
2359+
[C(RESULT_ACCESS)] = 0x0,
2360+
[C(RESULT_MISS)] = 0x0,
2361+
},
2362+
},
2363+
};
2364+
23222365
EVENT_ATTR_STR(topdown-fe-bound, td_fe_bound_tnt, "event=0x71,umask=0x0");
23232366
EVENT_ATTR_STR(topdown-retiring, td_retiring_tnt, "event=0xc2,umask=0x0");
23242367
EVENT_ATTR_STR(topdown-bad-spec, td_bad_spec_tnt, "event=0x73,umask=0x6");
@@ -2377,6 +2420,22 @@ static struct extra_reg intel_cmt_extra_regs[] __read_mostly = {
23772420
EVENT_EXTRA_END
23782421
};
23792422

2423+
static struct extra_reg intel_arw_extra_regs[] __read_mostly = {
2424+
/* must define OMR_X first, see intel_alt_er() */
2425+
INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OMR_0, 0xc0ffffffffffffffull, OMR_0),
2426+
INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OMR_1, 0xc0ffffffffffffffull, OMR_1),
2427+
INTEL_UEVENT_EXTRA_REG(0x04b7, MSR_OMR_2, 0xc0ffffffffffffffull, OMR_2),
2428+
INTEL_UEVENT_EXTRA_REG(0x08b7, MSR_OMR_3, 0xc0ffffffffffffffull, OMR_3),
2429+
INTEL_UEVENT_EXTRA_REG(0x01d4, MSR_OMR_0, 0xc0ffffffffffffffull, OMR_0),
2430+
INTEL_UEVENT_EXTRA_REG(0x02d4, MSR_OMR_1, 0xc0ffffffffffffffull, OMR_1),
2431+
INTEL_UEVENT_EXTRA_REG(0x04d4, MSR_OMR_2, 0xc0ffffffffffffffull, OMR_2),
2432+
INTEL_UEVENT_EXTRA_REG(0x08d4, MSR_OMR_3, 0xc0ffffffffffffffull, OMR_3),
2433+
INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x5d0),
2434+
INTEL_UEVENT_EXTRA_REG(0x0127, MSR_SNOOP_RSP_0, 0xffffffffffffffffull, SNOOP_0),
2435+
INTEL_UEVENT_EXTRA_REG(0x0227, MSR_SNOOP_RSP_1, 0xffffffffffffffffull, SNOOP_1),
2436+
EVENT_EXTRA_END
2437+
};
2438+
23802439
EVENT_ATTR_STR(topdown-fe-bound, td_fe_bound_skt, "event=0x9c,umask=0x01");
23812440
EVENT_ATTR_STR(topdown-retiring, td_retiring_skt, "event=0xc2,umask=0x02");
23822441
EVENT_ATTR_STR(topdown-be-bound, td_be_bound_skt, "event=0xa4,umask=0x02");
@@ -7410,6 +7469,19 @@ static __always_inline void intel_pmu_init_skt(struct pmu *pmu)
74107469
static_call_update(intel_pmu_enable_acr_event, intel_pmu_enable_acr);
74117470
}
74127471

7472+
static __always_inline void intel_pmu_init_arw(struct pmu *pmu)
7473+
{
7474+
intel_pmu_init_grt(pmu);
7475+
x86_pmu.flags &= ~PMU_FL_HAS_RSP_1;
7476+
x86_pmu.flags |= PMU_FL_HAS_OMR;
7477+
memcpy(hybrid_var(pmu, hw_cache_extra_regs),
7478+
arw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
7479+
hybrid(pmu, event_constraints) = intel_arw_event_constraints;
7480+
hybrid(pmu, pebs_constraints) = intel_arw_pebs_event_constraints;
7481+
hybrid(pmu, extra_regs) = intel_arw_extra_regs;
7482+
static_call_update(intel_pmu_enable_acr_event, intel_pmu_enable_acr);
7483+
}
7484+
74137485
__init int intel_pmu_init(void)
74147486
{
74157487
struct attribute **extra_skl_attr = &empty_attrs;
@@ -8250,6 +8322,33 @@ __init int intel_pmu_init(void)
82508322
name = "arrowlake_h_hybrid";
82518323
break;
82528324

8325+
case INTEL_NOVALAKE:
8326+
case INTEL_NOVALAKE_L:
8327+
pr_cont("Novalake Hybrid events, ");
8328+
name = "novalake_hybrid";
8329+
intel_pmu_init_hybrid(hybrid_big_small);
8330+
8331+
x86_pmu.pebs_latency_data = nvl_latency_data;
8332+
x86_pmu.get_event_constraints = mtl_get_event_constraints;
8333+
x86_pmu.hw_config = adl_hw_config;
8334+
8335+
td_attr = lnl_hybrid_events_attrs;
8336+
mem_attr = mtl_hybrid_mem_attrs;
8337+
tsx_attr = adl_hybrid_tsx_attrs;
8338+
extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
8339+
mtl_hybrid_extra_attr_rtm : mtl_hybrid_extra_attr;
8340+
8341+
/* Initialize big core specific PerfMon capabilities.*/
8342+
pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX];
8343+
intel_pmu_init_pnc(&pmu->pmu);
8344+
8345+
/* Initialize Atom core specific PerfMon capabilities.*/
8346+
pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX];
8347+
intel_pmu_init_arw(&pmu->pmu);
8348+
8349+
intel_pmu_pebs_data_source_lnl();
8350+
break;
8351+
82538352
default:
82548353
switch (x86_pmu.version) {
82558354
case 1:

‎arch/x86/events/intel/ds.c‎

Lines changed: 11 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1293,6 +1293,17 @@ struct event_constraint intel_grt_pebs_event_constraints[] = {
12931293
EVENT_CONSTRAINT_END
12941294
};
12951295

1296+
struct event_constraint intel_arw_pebs_event_constraints[] = {
1297+
/* Allow all events as PEBS with no flags */
1298+
INTEL_HYBRID_LAT_CONSTRAINT(0x5d0, 0xff),
1299+
INTEL_HYBRID_LAT_CONSTRAINT(0x6d0, 0xff),
1300+
INTEL_FLAGS_UEVENT_CONSTRAINT(0x01d4, 0x1),
1301+
INTEL_FLAGS_UEVENT_CONSTRAINT(0x02d4, 0x2),
1302+
INTEL_FLAGS_UEVENT_CONSTRAINT(0x04d4, 0x4),
1303+
INTEL_FLAGS_UEVENT_CONSTRAINT(0x08d4, 0x8),
1304+
EVENT_CONSTRAINT_END
1305+
};
1306+
12961307
struct event_constraint intel_nehalem_pebs_event_constraints[] = {
12971308
INTEL_PLD_CONSTRAINT(0x100b, 0xf), /* MEM_INST_RETIRED.* */
12981309
INTEL_FLAGS_EVENT_CONSTRAINT(0x0f, 0xf), /* MEM_UNCORE_RETIRED.* */

‎arch/x86/events/perf_event.h‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1680,6 +1680,8 @@ extern struct event_constraint intel_glp_pebs_event_constraints[];
16801680

16811681
extern struct event_constraint intel_grt_pebs_event_constraints[];
16821682

1683+
extern struct event_constraint intel_arw_pebs_event_constraints[];
1684+
16831685
extern struct event_constraint intel_nehalem_pebs_event_constraints[];
16841686

16851687
extern struct event_constraint intel_westmere_pebs_event_constraints[];

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