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| 1 | +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
| 2 | +%YAML 1.2 |
| 3 | +--- |
| 4 | +$id: http://devicetree.org/schemas/sound/fsl,spdif.yaml# |
| 5 | +$schema: http://devicetree.org/meta-schemas/core.yaml# |
| 6 | + |
| 7 | +title: Freescale Sony/Philips Digital Interface Format (S/PDIF) Controller |
| 8 | + |
| 9 | +maintainers: |
| 10 | + - Shengjiu Wang <shengjiu.wang@nxp.com> |
| 11 | + |
| 12 | +description: | |
| 13 | + The Freescale S/PDIF audio block is a stereo transceiver that allows the |
| 14 | + processor to receive and transmit digital audio via an coaxial cable or |
| 15 | + a fibre cable. |
| 16 | +
|
| 17 | +properties: |
| 18 | + compatible: |
| 19 | + enum: |
| 20 | + - fsl,imx35-spdif |
| 21 | + - fsl,vf610-spdif |
| 22 | + - fsl,imx6sx-spdif |
| 23 | + |
| 24 | + reg: |
| 25 | + maxItems: 1 |
| 26 | + |
| 27 | + interrupts: |
| 28 | + maxItems: 1 |
| 29 | + |
| 30 | + dmas: |
| 31 | + items: |
| 32 | + - description: DMA controller phandle and request line for RX |
| 33 | + - description: DMA controller phandle and request line for TX |
| 34 | + |
| 35 | + dma-names: |
| 36 | + items: |
| 37 | + - const: rx |
| 38 | + - const: tx |
| 39 | + |
| 40 | + clocks: |
| 41 | + items: |
| 42 | + - description: The core clock of spdif controller. |
| 43 | + - description: Clock for tx0 and rx0. |
| 44 | + - description: Clock for tx1 and rx1. |
| 45 | + - description: Clock for tx2 and rx2. |
| 46 | + - description: Clock for tx3 and rx3. |
| 47 | + - description: Clock for tx4 and rx4. |
| 48 | + - description: Clock for tx5 and rx5. |
| 49 | + - description: Clock for tx6 and rx6. |
| 50 | + - description: Clock for tx7 and rx7. |
| 51 | + - description: The spba clock is required when SPDIF is placed as a bus |
| 52 | + slave of the Shared Peripheral Bus and when two or more bus masters |
| 53 | + (CPU, DMA or DSP) try to access it. This property is optional depending |
| 54 | + on the SoC design. |
| 55 | + minItems: 9 |
| 56 | + |
| 57 | + clock-names: |
| 58 | + items: |
| 59 | + - const: core |
| 60 | + - const: rxtx0 |
| 61 | + - const: rxtx1 |
| 62 | + - const: rxtx2 |
| 63 | + - const: rxtx3 |
| 64 | + - const: rxtx4 |
| 65 | + - const: rxtx5 |
| 66 | + - const: rxtx6 |
| 67 | + - const: rxtx7 |
| 68 | + - const: spba |
| 69 | + minItems: 9 |
| 70 | + |
| 71 | + big-endian: |
| 72 | + $ref: /schemas/types.yaml#/definitions/flag |
| 73 | + description: | |
| 74 | + If this property is absent, the native endian mode will be in use |
| 75 | + as default, or the big endian mode will be in use for all the device |
| 76 | + registers. Set this flag for HCDs with big endian descriptors and big |
| 77 | + endian registers. |
| 78 | +
|
| 79 | +required: |
| 80 | + - compatible |
| 81 | + - reg |
| 82 | + - interrupts |
| 83 | + - dmas |
| 84 | + - dma-names |
| 85 | + - clocks |
| 86 | + - clock-names |
| 87 | + |
| 88 | +additionalProperties: false |
| 89 | + |
| 90 | +examples: |
| 91 | + - | |
| 92 | + spdif@2004000 { |
| 93 | + compatible = "fsl,imx35-spdif"; |
| 94 | + reg = <0x02004000 0x4000>; |
| 95 | + interrupts = <0 52 0x04>; |
| 96 | + dmas = <&sdma 14 18 0>, |
| 97 | + <&sdma 15 18 0>; |
| 98 | + dma-names = "rx", "tx"; |
| 99 | + clocks = <&clks 197>, <&clks 3>, |
| 100 | + <&clks 197>, <&clks 107>, |
| 101 | + <&clks 0>, <&clks 118>, |
| 102 | + <&clks 62>, <&clks 139>, |
| 103 | + <&clks 0>; |
| 104 | + clock-names = "core", "rxtx0", |
| 105 | + "rxtx1", "rxtx2", |
| 106 | + "rxtx3", "rxtx4", |
| 107 | + "rxtx5", "rxtx6", |
| 108 | + "rxtx7"; |
| 109 | + big-endian; |
| 110 | + }; |
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