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Thomas Richterhcahca
Thomas Richter
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hcahca
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s390/cpumf: add new extended counter set for IBM z16
Export the extended counter set counters of the IBM z16 via sysfs. Signed-off-by: Thomas Richter <tmricht@linux.ibm.com> Acked-by: Sumanth Korikkar <sumanthk@linux.ibm.com> Signed-off-by: Heiko Carstens <hca@linux.ibm.com>
1 parent 63678ee commit c9311de

1 file changed

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‎arch/s390/kernel/perf_cpum_cf_events.c‎

Lines changed: 148 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -295,6 +295,76 @@ CPUMF_EVENT_ATTR(cf_z15, DFLT_CC, 0x00108);
295295
CPUMF_EVENT_ATTR(cf_z15, DFLT_CCFINISH, 0x00109);
296296
CPUMF_EVENT_ATTR(cf_z15, MT_DIAG_CYCLES_ONE_THR_ACTIVE, 0x01c0);
297297
CPUMF_EVENT_ATTR(cf_z15, MT_DIAG_CYCLES_TWO_THR_ACTIVE, 0x01c1);
298+
CPUMF_EVENT_ATTR(cf_z16, L1D_RO_EXCL_WRITES, 0x0080);
299+
CPUMF_EVENT_ATTR(cf_z16, DTLB2_WRITES, 0x0081);
300+
CPUMF_EVENT_ATTR(cf_z16, DTLB2_MISSES, 0x0082);
301+
CPUMF_EVENT_ATTR(cf_z16, CRSTE_1MB_WRITES, 0x0083);
302+
CPUMF_EVENT_ATTR(cf_z16, DTLB2_GPAGE_WRITES, 0x0084);
303+
CPUMF_EVENT_ATTR(cf_z16, ITLB2_WRITES, 0x0086);
304+
CPUMF_EVENT_ATTR(cf_z16, ITLB2_MISSES, 0x0087);
305+
CPUMF_EVENT_ATTR(cf_z16, TLB2_PTE_WRITES, 0x0089);
306+
CPUMF_EVENT_ATTR(cf_z16, TLB2_CRSTE_WRITES, 0x008a);
307+
CPUMF_EVENT_ATTR(cf_z16, TLB2_ENGINES_BUSY, 0x008b);
308+
CPUMF_EVENT_ATTR(cf_z16, TX_C_TEND, 0x008c);
309+
CPUMF_EVENT_ATTR(cf_z16, TX_NC_TEND, 0x008d);
310+
CPUMF_EVENT_ATTR(cf_z16, L1C_TLB2_MISSES, 0x008f);
311+
CPUMF_EVENT_ATTR(cf_z16, DCW_REQ, 0x0091);
312+
CPUMF_EVENT_ATTR(cf_z16, DCW_REQ_IV, 0x0092);
313+
CPUMF_EVENT_ATTR(cf_z16, DCW_REQ_CHIP_HIT, 0x0093);
314+
CPUMF_EVENT_ATTR(cf_z16, DCW_REQ_DRAWER_HIT, 0x0094);
315+
CPUMF_EVENT_ATTR(cf_z16, DCW_ON_CHIP, 0x0095);
316+
CPUMF_EVENT_ATTR(cf_z16, DCW_ON_CHIP_IV, 0x0096);
317+
CPUMF_EVENT_ATTR(cf_z16, DCW_ON_CHIP_CHIP_HIT, 0x0097);
318+
CPUMF_EVENT_ATTR(cf_z16, DCW_ON_CHIP_DRAWER_HIT, 0x0098);
319+
CPUMF_EVENT_ATTR(cf_z16, DCW_ON_MODULE, 0x0099);
320+
CPUMF_EVENT_ATTR(cf_z16, DCW_ON_DRAWER, 0x009a);
321+
CPUMF_EVENT_ATTR(cf_z16, DCW_OFF_DRAWER, 0x009b);
322+
CPUMF_EVENT_ATTR(cf_z16, DCW_ON_CHIP_MEMORY, 0x009c);
323+
CPUMF_EVENT_ATTR(cf_z16, DCW_ON_MODULE_MEMORY, 0x009d);
324+
CPUMF_EVENT_ATTR(cf_z16, DCW_ON_DRAWER_MEMORY, 0x009e);
325+
CPUMF_EVENT_ATTR(cf_z16, DCW_OFF_DRAWER_MEMORY, 0x009f);
326+
CPUMF_EVENT_ATTR(cf_z16, IDCW_ON_MODULE_IV, 0x00a0);
327+
CPUMF_EVENT_ATTR(cf_z16, IDCW_ON_MODULE_CHIP_HIT, 0x00a1);
328+
CPUMF_EVENT_ATTR(cf_z16, IDCW_ON_MODULE_DRAWER_HIT, 0x00a2);
329+
CPUMF_EVENT_ATTR(cf_z16, IDCW_ON_DRAWER_IV, 0x00a3);
330+
CPUMF_EVENT_ATTR(cf_z16, IDCW_ON_DRAWER_CHIP_HIT, 0x00a4);
331+
CPUMF_EVENT_ATTR(cf_z16, IDCW_ON_DRAWER_DRAWER_HIT, 0x00a5);
332+
CPUMF_EVENT_ATTR(cf_z16, IDCW_OFF_DRAWER_IV, 0x00a6);
333+
CPUMF_EVENT_ATTR(cf_z16, IDCW_OFF_DRAWER_CHIP_HIT, 0x00a7);
334+
CPUMF_EVENT_ATTR(cf_z16, IDCW_OFF_DRAWER_DRAWER_HIT, 0x00a8);
335+
CPUMF_EVENT_ATTR(cf_z16, ICW_REQ, 0x00a9);
336+
CPUMF_EVENT_ATTR(cf_z16, ICW_REQ_IV, 0x00aa);
337+
CPUMF_EVENT_ATTR(cf_z16, ICW_REQ_CHIP_HIT, 0x00ab);
338+
CPUMF_EVENT_ATTR(cf_z16, ICW_REQ_DRAWER_HIT, 0x00ac);
339+
CPUMF_EVENT_ATTR(cf_z16, ICW_ON_CHIP, 0x00ad);
340+
CPUMF_EVENT_ATTR(cf_z16, ICW_ON_CHIP_IV, 0x00ae);
341+
CPUMF_EVENT_ATTR(cf_z16, ICW_ON_CHIP_CHIP_HIT, 0x00af);
342+
CPUMF_EVENT_ATTR(cf_z16, ICW_ON_CHIP_DRAWER_HIT, 0x00b0);
343+
CPUMF_EVENT_ATTR(cf_z16, ICW_ON_MODULE, 0x00b1);
344+
CPUMF_EVENT_ATTR(cf_z16, ICW_ON_DRAWER, 0x00b2);
345+
CPUMF_EVENT_ATTR(cf_z16, ICW_OFF_DRAWER, 0x00b3);
346+
CPUMF_EVENT_ATTR(cf_z16, ICW_ON_CHIP_MEMORY, 0x00b4);
347+
CPUMF_EVENT_ATTR(cf_z16, ICW_ON_MODULE_MEMORY, 0x00b5);
348+
CPUMF_EVENT_ATTR(cf_z16, ICW_ON_DRAWER_MEMORY, 0x00b6);
349+
CPUMF_EVENT_ATTR(cf_z16, ICW_OFF_DRAWER_MEMORY, 0x00b7);
350+
CPUMF_EVENT_ATTR(cf_z16, BCD_DFP_EXECUTION_SLOTS, 0x00e0);
351+
CPUMF_EVENT_ATTR(cf_z16, VX_BCD_EXECUTION_SLOTS, 0x00e1);
352+
CPUMF_EVENT_ATTR(cf_z16, DECIMAL_INSTRUCTIONS, 0x00e2);
353+
CPUMF_EVENT_ATTR(cf_z16, LAST_HOST_TRANSLATIONS, 0x00e8);
354+
CPUMF_EVENT_ATTR(cf_z16, TX_NC_TABORT, 0x00f4);
355+
CPUMF_EVENT_ATTR(cf_z16, TX_C_TABORT_NO_SPECIAL, 0x00f5);
356+
CPUMF_EVENT_ATTR(cf_z16, TX_C_TABORT_SPECIAL, 0x00f6);
357+
CPUMF_EVENT_ATTR(cf_z16, DFLT_ACCESS, 0x00f8);
358+
CPUMF_EVENT_ATTR(cf_z16, DFLT_CYCLES, 0x00fd);
359+
CPUMF_EVENT_ATTR(cf_z16, SORTL, 0x0100);
360+
CPUMF_EVENT_ATTR(cf_z16, DFLT_CC, 0x0109);
361+
CPUMF_EVENT_ATTR(cf_z16, DFLT_CCFINISH, 0x010a);
362+
CPUMF_EVENT_ATTR(cf_z16, NNPA_INVOCATIONS, 0x010b);
363+
CPUMF_EVENT_ATTR(cf_z16, NNPA_COMPLETIONS, 0x010c);
364+
CPUMF_EVENT_ATTR(cf_z16, NNPA_WAIT_LOCK, 0x010d);
365+
CPUMF_EVENT_ATTR(cf_z16, NNPA_HOLD_LOCK, 0x010e);
366+
CPUMF_EVENT_ATTR(cf_z16, MT_DIAG_CYCLES_ONE_THR_ACTIVE, 0x01c0);
367+
CPUMF_EVENT_ATTR(cf_z16, MT_DIAG_CYCLES_TWO_THR_ACTIVE, 0x01c1);
298368

299369
static struct attribute *cpumcf_fvn1_pmu_event_attr[] __initdata = {
300370
CPUMF_EVENT_PTR(cf_fvn1, CPU_CYCLES),
@@ -635,6 +705,80 @@ static struct attribute *cpumcf_z15_pmu_event_attr[] __initdata = {
635705
NULL,
636706
};
637707

708+
static struct attribute *cpumcf_z16_pmu_event_attr[] __initdata = {
709+
CPUMF_EVENT_PTR(cf_z16, L1D_RO_EXCL_WRITES),
710+
CPUMF_EVENT_PTR(cf_z16, DTLB2_WRITES),
711+
CPUMF_EVENT_PTR(cf_z16, DTLB2_MISSES),
712+
CPUMF_EVENT_PTR(cf_z16, CRSTE_1MB_WRITES),
713+
CPUMF_EVENT_PTR(cf_z16, DTLB2_GPAGE_WRITES),
714+
CPUMF_EVENT_PTR(cf_z16, ITLB2_WRITES),
715+
CPUMF_EVENT_PTR(cf_z16, ITLB2_MISSES),
716+
CPUMF_EVENT_PTR(cf_z16, TLB2_PTE_WRITES),
717+
CPUMF_EVENT_PTR(cf_z16, TLB2_CRSTE_WRITES),
718+
CPUMF_EVENT_PTR(cf_z16, TLB2_ENGINES_BUSY),
719+
CPUMF_EVENT_PTR(cf_z16, TX_C_TEND),
720+
CPUMF_EVENT_PTR(cf_z16, TX_NC_TEND),
721+
CPUMF_EVENT_PTR(cf_z16, L1C_TLB2_MISSES),
722+
CPUMF_EVENT_PTR(cf_z16, DCW_REQ),
723+
CPUMF_EVENT_PTR(cf_z16, DCW_REQ_IV),
724+
CPUMF_EVENT_PTR(cf_z16, DCW_REQ_CHIP_HIT),
725+
CPUMF_EVENT_PTR(cf_z16, DCW_REQ_DRAWER_HIT),
726+
CPUMF_EVENT_PTR(cf_z16, DCW_ON_CHIP),
727+
CPUMF_EVENT_PTR(cf_z16, DCW_ON_CHIP_IV),
728+
CPUMF_EVENT_PTR(cf_z16, DCW_ON_CHIP_CHIP_HIT),
729+
CPUMF_EVENT_PTR(cf_z16, DCW_ON_CHIP_DRAWER_HIT),
730+
CPUMF_EVENT_PTR(cf_z16, DCW_ON_MODULE),
731+
CPUMF_EVENT_PTR(cf_z16, DCW_ON_DRAWER),
732+
CPUMF_EVENT_PTR(cf_z16, DCW_OFF_DRAWER),
733+
CPUMF_EVENT_PTR(cf_z16, DCW_ON_CHIP_MEMORY),
734+
CPUMF_EVENT_PTR(cf_z16, DCW_ON_MODULE_MEMORY),
735+
CPUMF_EVENT_PTR(cf_z16, DCW_ON_DRAWER_MEMORY),
736+
CPUMF_EVENT_PTR(cf_z16, DCW_OFF_DRAWER_MEMORY),
737+
CPUMF_EVENT_PTR(cf_z16, IDCW_ON_MODULE_IV),
738+
CPUMF_EVENT_PTR(cf_z16, IDCW_ON_MODULE_CHIP_HIT),
739+
CPUMF_EVENT_PTR(cf_z16, IDCW_ON_MODULE_DRAWER_HIT),
740+
CPUMF_EVENT_PTR(cf_z16, IDCW_ON_DRAWER_IV),
741+
CPUMF_EVENT_PTR(cf_z16, IDCW_ON_DRAWER_CHIP_HIT),
742+
CPUMF_EVENT_PTR(cf_z16, IDCW_ON_DRAWER_DRAWER_HIT),
743+
CPUMF_EVENT_PTR(cf_z16, IDCW_OFF_DRAWER_IV),
744+
CPUMF_EVENT_PTR(cf_z16, IDCW_OFF_DRAWER_CHIP_HIT),
745+
CPUMF_EVENT_PTR(cf_z16, IDCW_OFF_DRAWER_DRAWER_HIT),
746+
CPUMF_EVENT_PTR(cf_z16, ICW_REQ),
747+
CPUMF_EVENT_PTR(cf_z16, ICW_REQ_IV),
748+
CPUMF_EVENT_PTR(cf_z16, ICW_REQ_CHIP_HIT),
749+
CPUMF_EVENT_PTR(cf_z16, ICW_REQ_DRAWER_HIT),
750+
CPUMF_EVENT_PTR(cf_z16, ICW_ON_CHIP),
751+
CPUMF_EVENT_PTR(cf_z16, ICW_ON_CHIP_IV),
752+
CPUMF_EVENT_PTR(cf_z16, ICW_ON_CHIP_CHIP_HIT),
753+
CPUMF_EVENT_PTR(cf_z16, ICW_ON_CHIP_DRAWER_HIT),
754+
CPUMF_EVENT_PTR(cf_z16, ICW_ON_MODULE),
755+
CPUMF_EVENT_PTR(cf_z16, ICW_ON_DRAWER),
756+
CPUMF_EVENT_PTR(cf_z16, ICW_OFF_DRAWER),
757+
CPUMF_EVENT_PTR(cf_z16, ICW_ON_CHIP_MEMORY),
758+
CPUMF_EVENT_PTR(cf_z16, ICW_ON_MODULE_MEMORY),
759+
CPUMF_EVENT_PTR(cf_z16, ICW_ON_DRAWER_MEMORY),
760+
CPUMF_EVENT_PTR(cf_z16, ICW_OFF_DRAWER_MEMORY),
761+
CPUMF_EVENT_PTR(cf_z16, BCD_DFP_EXECUTION_SLOTS),
762+
CPUMF_EVENT_PTR(cf_z16, VX_BCD_EXECUTION_SLOTS),
763+
CPUMF_EVENT_PTR(cf_z16, DECIMAL_INSTRUCTIONS),
764+
CPUMF_EVENT_PTR(cf_z16, LAST_HOST_TRANSLATIONS),
765+
CPUMF_EVENT_PTR(cf_z16, TX_NC_TABORT),
766+
CPUMF_EVENT_PTR(cf_z16, TX_C_TABORT_NO_SPECIAL),
767+
CPUMF_EVENT_PTR(cf_z16, TX_C_TABORT_SPECIAL),
768+
CPUMF_EVENT_PTR(cf_z16, DFLT_ACCESS),
769+
CPUMF_EVENT_PTR(cf_z16, DFLT_CYCLES),
770+
CPUMF_EVENT_PTR(cf_z16, SORTL),
771+
CPUMF_EVENT_PTR(cf_z16, DFLT_CC),
772+
CPUMF_EVENT_PTR(cf_z16, DFLT_CCFINISH),
773+
CPUMF_EVENT_PTR(cf_z16, NNPA_INVOCATIONS),
774+
CPUMF_EVENT_PTR(cf_z16, NNPA_COMPLETIONS),
775+
CPUMF_EVENT_PTR(cf_z16, NNPA_WAIT_LOCK),
776+
CPUMF_EVENT_PTR(cf_z16, NNPA_HOLD_LOCK),
777+
CPUMF_EVENT_PTR(cf_z16, MT_DIAG_CYCLES_ONE_THR_ACTIVE),
778+
CPUMF_EVENT_PTR(cf_z16, MT_DIAG_CYCLES_TWO_THR_ACTIVE),
779+
NULL,
780+
};
781+
638782
/* END: CPUM_CF COUNTER DEFINITIONS ===================================== */
639783

640784
static struct attribute_group cpumcf_pmu_events_group = {
@@ -749,6 +893,10 @@ __init const struct attribute_group **cpumf_cf_event_group(void)
749893
case 0x8562:
750894
model = cpumcf_z15_pmu_event_attr;
751895
break;
896+
case 0x3931:
897+
case 0x3932:
898+
model = cpumcf_z16_pmu_event_attr;
899+
break;
752900
default:
753901
model = none;
754902
break;

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