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Add PM4125 audio codec driver
Merge series from Alexey Klimov <alexey.klimov@linaro.org>: PMICs like PM4125 have in-built audio codec IC. The series here adds support for this codec driver: DT bindings and codec driver itself that consists mainly of two parts: soundwire devices and codec part itself. This audio codec can be found on platforms like QCM2290 and on Qualcomm QRB2210 RB1 board. We are working on this together with Srini (srinivas.kandagatla@oss.qualcomm.com or srini@kernel.org). This driver also has a bit limited support for concurrent playback, since line out path is connected to left input channel.
2 parents 5b65120 + 88d0d17 commit c996429

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Documentation/ABI/testing/sysfs-devices-system-cpu

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@@ -586,6 +586,7 @@ What: /sys/devices/system/cpu/vulnerabilities
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/sys/devices/system/cpu/vulnerabilities/srbds
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/sys/devices/system/cpu/vulnerabilities/tsa
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/sys/devices/system/cpu/vulnerabilities/tsx_async_abort
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/sys/devices/system/cpu/vulnerabilities/vmscape
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Date: January 2018
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Contact: Linux kernel mailing list <linux-kernel@vger.kernel.org>
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Description: Information about CPU vulnerabilities

Documentation/admin-guide/hw-vuln/index.rst

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@@ -26,3 +26,4 @@ are configurable at compile, boot or run time.
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rsb
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old_microcode
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indirect-target-selection
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vmscape
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.. SPDX-License-Identifier: GPL-2.0
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VMSCAPE
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=======
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VMSCAPE is a vulnerability that may allow a guest to influence the branch
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prediction in host userspace. It particularly affects hypervisors like QEMU.
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Even if a hypervisor may not have any sensitive data like disk encryption keys,
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guest-userspace may be able to attack the guest-kernel using the hypervisor as
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a confused deputy.
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Affected processors
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-------------------
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The following CPU families are affected by VMSCAPE:
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**Intel processors:**
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- Skylake generation (Parts without Enhanced-IBRS)
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- Cascade Lake generation - (Parts affected by ITS guest/host separation)
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- Alder Lake and newer (Parts affected by BHI)
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Note that, BHI affected parts that use BHB clearing software mitigation e.g.
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Icelake are not vulnerable to VMSCAPE.
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**AMD processors:**
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- Zen series (families 0x17, 0x19, 0x1a)
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** Hygon processors:**
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- Family 0x18
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Mitigation
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----------
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Conditional IBPB
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----------------
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Kernel tracks when a CPU has run a potentially malicious guest and issues an
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IBPB before the first exit to userspace after VM-exit. If userspace did not run
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between VM-exit and the next VM-entry, no IBPB is issued.
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Note that the existing userspace mitigation against Spectre-v2 is effective in
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protecting the userspace. They are insufficient to protect the userspace VMMs
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from a malicious guest. This is because Spectre-v2 mitigations are applied at
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context switch time, while the userspace VMM can run after a VM-exit without a
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context switch.
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Vulnerability enumeration and mitigation is not applied inside a guest. This is
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because nested hypervisors should already be deploying IBPB to isolate
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themselves from nested guests.
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SMT considerations
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------------------
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When Simultaneous Multi-Threading (SMT) is enabled, hypervisors can be
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vulnerable to cross-thread attacks. For complete protection against VMSCAPE
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attacks in SMT environments, STIBP should be enabled.
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The kernel will issue a warning if SMT is enabled without adequate STIBP
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protection. Warning is not issued when:
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- SMT is disabled
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- STIBP is enabled system-wide
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- Intel eIBRS is enabled (which implies STIBP protection)
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System information and options
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------------------------------
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The sysfs file showing VMSCAPE mitigation status is:
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/sys/devices/system/cpu/vulnerabilities/vmscape
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The possible values in this file are:
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* 'Not affected':
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The processor is not vulnerable to VMSCAPE attacks.
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* 'Vulnerable':
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The processor is vulnerable and no mitigation has been applied.
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* 'Mitigation: IBPB before exit to userspace':
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Conditional IBPB mitigation is enabled. The kernel tracks when a CPU has
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run a potentially malicious guest and issues an IBPB before the first
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exit to userspace after VM-exit.
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* 'Mitigation: IBPB on VMEXIT':
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IBPB is issued on every VM-exit. This occurs when other mitigations like
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RETBLEED or SRSO are already issuing IBPB on VM-exit.
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Mitigation control on the kernel command line
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----------------------------------------------
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The mitigation can be controlled via the ``vmscape=`` command line parameter:
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* ``vmscape=off``:
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Disable the VMSCAPE mitigation.
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* ``vmscape=ibpb``:
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Enable conditional IBPB mitigation (default when CONFIG_MITIGATION_VMSCAPE=y).
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* ``vmscape=force``:
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Force vulnerability detection and mitigation even on processors that are
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not known to be affected.

Documentation/admin-guide/kernel-parameters.txt

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srbds=off [X86,INTEL]
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ssbd=force-off [ARM64]
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tsx_async_abort=off [X86]
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vmscape=off [X86]
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Exceptions:
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This does not have any effect on
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vmpoff= [KNL,S390] Perform z/VM CP command after power off.
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Format: <command>
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vmscape= [X86] Controls mitigation for VMscape attacks.
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VMscape attacks can leak information from a userspace
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hypervisor to a guest via speculative side-channels.
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off - disable the mitigation
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ibpb - use Indirect Branch Prediction Barrier
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(IBPB) mitigation (default)
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force - force vulnerability detection even on
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unaffected processors
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vsyscall= [X86-64,EARLY]
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Controls the behavior of vsyscalls (i.e. calls to
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fixed addresses of 0xffffffffff600x00 from legacy

Documentation/devicetree/bindings/dma/qcom,bam-dma.yaml

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anyOf:
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- required:
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- qcom,powered-remotely
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- num-channels
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- qcom,num-ees
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- required:
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- qcom,controlled-remotely
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- num-channels
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- qcom,num-ees
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- required:
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- clocks
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- clock-names

Documentation/devicetree/bindings/phy/marvell,comphy-cp110.yaml

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const: 0
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clocks:
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minItems: 1
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maxItems: 3
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description: Reference clocks for CP110; MG clock, MG Core clock, AXI clock
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clock-names:
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items:
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- const: mg_clk
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- const: mg_core_clk
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- const: axi_clk
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minItems: 1
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maxItems: 3
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marvell,system-controller:
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description: Phandle to the Marvell system controller (CP110 only)
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$ref: /schemas/types.yaml#/definitions/phandle
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patternProperties:
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'^phy@[0-2]$':
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'^phy@[0-5]$':
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description: A COMPHY lane child node
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type: object
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additionalProperties: false
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properties:
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reg:
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description: COMPHY lane number
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maximum: 5
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'#phy-cells':
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const: 1
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connector:
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type: object
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required:
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- '#phy-cells'
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then:
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properties:
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clocks: false
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clock-names: false
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clocks:
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maxItems: 1
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clock-names:
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const: xtal
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required:
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- reg-names
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else:
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properties:
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clocks:
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minItems: 3
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clock-names:
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items:
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- const: mg_clk
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- const: mg_core_clk
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- const: axi_clk
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required:
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- marvell,system-controller
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Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml

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compatible:
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contains:
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enum:
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- qcom,sa8775p-qmp-gen4x2-pcie-phy
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- qcom,sa8775p-qmp-gen4x4-pcie-phy
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- qcom,sc8280xp-qmp-gen3x1-pcie-phy
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- qcom,sc8280xp-qmp-gen3x2-pcie-phy
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- qcom,sc8280xp-qmp-gen3x4-pcie-phy
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contains:
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enum:
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- qcom,qcs8300-qmp-gen4x2-pcie-phy
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- qcom,sa8775p-qmp-gen4x2-pcie-phy
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- qcom,sa8775p-qmp-gen4x4-pcie-phy
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then:
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properties:
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clocks:

Documentation/devicetree/bindings/serial/8250.yaml

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oneOf:
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- required: [ clock-frequency ]
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- required: [ clocks ]
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- if:
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properties:
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compatible:
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items:
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- const: uartclk
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- const: reg
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else:
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- if:
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properties:
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compatible:
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contains:
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const: spacemit,k1-uart
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then:
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properties:
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clock-names:
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items:
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- const: core
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- const: bus
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- if:
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properties:
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compatible:
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contains:
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enum:
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- spacemit,k1-uart
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- nxp,lpc1850-uart
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then:
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required:
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- clocks
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- clock-names
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properties:
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clocks:
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minItems: 2
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clock-names:
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minItems: 2
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else:
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properties:
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clocks:
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maxItems: 1
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clock-names:
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maxItems: 1
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properties:
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compatible:
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minItems: 1
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maxItems: 2
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oneOf:
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- enum:
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- main
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- uart
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- items:
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- const: core
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- const: bus
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- reg
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- interrupts
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if:
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properties:
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compatible:
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contains:
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enum:
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- spacemit,k1-uart
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- nxp,lpc1850-uart
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then:
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required:
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- clocks
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- clock-names
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properties:
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clocks:
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minItems: 2
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clock-names:
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minItems: 2
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else:
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properties:
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clocks:
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maxItems: 1
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clock-names:
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maxItems: 1
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unevaluatedProperties: false
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examples:

Documentation/devicetree/bindings/serial/brcm,bcm7271-uart.yaml

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clocks:
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clock-names:
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const: sw_baud

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