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cxl: update names for interleave ways conversion macros
Change names for interleave ways macros to clearly indicate which variable is encoded and which is the actual ways value. ways == interleave ways eiw == encoded interleave ways Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Signed-off-by: Dave Jiang <dave.jiang@intel.com> Link: https://lore.kernel.org/r/167027516228.3124679.11265039496968588580.stgit@djiang5-desk3.ch.intel.com Signed-off-by: Dan Williams <dan.j.williams@intel.com>
1 parent 83351dd commit c99b2e8

4 files changed

Lines changed: 16 additions & 16 deletions

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drivers/cxl/acpi.c

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -34,7 +34,7 @@ static int cxl_xor_calc_n(u64 hpa, struct cxl_cxims_data *cximsd, int iw,
3434
}
3535
/* IW: 3,6,12 add a modulo calculation to 'n' */
3636
if (!is_power_of_2(iw)) {
37-
if (ways_to_cxl(iw, &eiw))
37+
if (ways_to_eiw(iw, &eiw))
3838
return -1;
3939
hpa &= GENMASK_ULL(51, eiw + ig);
4040
n |= do_div(hpa, 3) << i;
@@ -161,7 +161,7 @@ static int cxl_acpi_cfmws_verify(struct device *dev,
161161
return -EINVAL;
162162
}
163163

164-
rc = cxl_to_ways(cfmws->interleave_ways, &ways);
164+
rc = eiw_to_ways(cfmws->interleave_ways, &ways);
165165
if (rc) {
166166
dev_err(dev, "CFMWS Interleave Ways (%d) invalid\n",
167167
cfmws->interleave_ways);
@@ -221,7 +221,7 @@ static int cxl_parse_cfmws(union acpi_subtable_headers *header, void *arg,
221221
return 0;
222222
}
223223

224-
rc = cxl_to_ways(cfmws->interleave_ways, &ways);
224+
rc = eiw_to_ways(cfmws->interleave_ways, &ways);
225225
if (rc)
226226
return rc;
227227
rc = eig_to_granularity(cfmws->granularity, &ig);

drivers/cxl/core/hdm.c

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -494,7 +494,7 @@ static void cxld_set_interleave(struct cxl_decoder *cxld, u32 *ctrl)
494494
* Input validation ensures these warns never fire, but otherwise
495495
* suppress unititalized variable usage warnings.
496496
*/
497-
if (WARN_ONCE(ways_to_cxl(cxld->interleave_ways, &eiw),
497+
if (WARN_ONCE(ways_to_eiw(cxld->interleave_ways, &eiw),
498498
"invalid interleave_ways: %d\n", cxld->interleave_ways))
499499
return;
500500
if (WARN_ONCE(granularity_to_eig(cxld->interleave_granularity, &eig),
@@ -741,8 +741,8 @@ static int init_hdm_decoder(struct cxl_port *port, struct cxl_decoder *cxld,
741741
}
742742
cxld->target_type = CXL_DECODER_EXPANDER;
743743
}
744-
rc = cxl_to_ways(FIELD_GET(CXL_HDM_DECODER0_CTRL_IW_MASK, ctrl),
745-
&cxld->interleave_ways);
744+
rc = eiw_to_ways(FIELD_GET(CXL_HDM_DECODER0_CTRL_IW_MASK, ctrl),
745+
&cxld->interleave_ways);
746746
if (rc) {
747747
dev_warn(&port->dev,
748748
"decoder%d.%d: Invalid interleave ways (ctrl: %#x)\n",

drivers/cxl/core/region.c

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -324,7 +324,7 @@ static ssize_t interleave_ways_store(struct device *dev,
324324
if (rc)
325325
return rc;
326326

327-
rc = ways_to_cxl(val, &iw);
327+
rc = ways_to_eiw(val, &iw);
328328
if (rc)
329329
return rc;
330330

@@ -1036,7 +1036,7 @@ static int cxl_port_setup_targets(struct cxl_port *port,
10361036
return rc;
10371037
}
10381038

1039-
rc = ways_to_cxl(parent_iw, &peiw);
1039+
rc = ways_to_eiw(parent_iw, &peiw);
10401040
if (rc) {
10411041
dev_dbg(&cxlr->dev, "%s:%s: invalid parent interleave: %d\n",
10421042
dev_name(parent_port->uport),
@@ -1045,7 +1045,7 @@ static int cxl_port_setup_targets(struct cxl_port *port,
10451045
}
10461046

10471047
iw = cxl_rr->nr_targets;
1048-
rc = ways_to_cxl(iw, &eiw);
1048+
rc = ways_to_eiw(iw, &eiw);
10491049
if (rc) {
10501050
dev_dbg(&cxlr->dev, "%s:%s: invalid port interleave: %d\n",
10511051
dev_name(port->uport), dev_name(&port->dev), iw);

drivers/cxl/cxl.h

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -83,14 +83,14 @@ static inline int eig_to_granularity(u16 eig, unsigned int *granularity)
8383
}
8484

8585
/* Encode defined in CXL ECN "3, 6, 12 and 16-way memory Interleaving" */
86-
static inline int cxl_to_ways(u8 eniw, unsigned int *val)
86+
static inline int eiw_to_ways(u8 eiw, unsigned int *ways)
8787
{
88-
switch (eniw) {
88+
switch (eiw) {
8989
case 0 ... 4:
90-
*val = 1 << eniw;
90+
*ways = 1 << eiw;
9191
break;
9292
case 8 ... 10:
93-
*val = 3 << (eniw - 8);
93+
*ways = 3 << (eiw - 8);
9494
break;
9595
default:
9696
return -EINVAL;
@@ -108,20 +108,20 @@ static inline int granularity_to_eig(int granularity, u16 *eig)
108108
return 0;
109109
}
110110

111-
static inline int ways_to_cxl(unsigned int ways, u8 *iw)
111+
static inline int ways_to_eiw(unsigned int ways, u8 *eiw)
112112
{
113113
if (ways > 16)
114114
return -EINVAL;
115115
if (is_power_of_2(ways)) {
116-
*iw = ilog2(ways);
116+
*eiw = ilog2(ways);
117117
return 0;
118118
}
119119
if (ways % 3)
120120
return -EINVAL;
121121
ways /= 3;
122122
if (!is_power_of_2(ways))
123123
return -EINVAL;
124-
*iw = ilog2(ways) + 8;
124+
*eiw = ilog2(ways) + 8;
125125
return 0;
126126
}
127127

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