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mbrost05Thomas Hellström
mbrost05
authored and
Thomas Hellström
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drm/xe: Make all GuC ABI shift values unsigned
All GuC ABI definitions are unsigned and not defining as unsigned is causing build errors [1]. [1] https://lore.kernel.org/all/20240123111235.3097079-1-geert@linux-m68k.org/ Fixes: dd08ebf ("drm/xe: Introduce a new DRM driver for Intel GPUs") Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com> Signed-off-by: Matthew Brost <matthew.brost@intel.com> Reviewed-by: Thomas Hellström <thomas.hellstrom@linux.intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240131025424.2087936-1-matthew.brost@intel.com (cherry picked from commit d83d8ae) Signed-off-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
1 parent ed2bdf3 commit c9cfed2

5 files changed

Lines changed: 21 additions & 21 deletions

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‎drivers/gpu/drm/xe/abi/guc_actions_abi.h‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -50,8 +50,8 @@
5050

5151
#define HOST2GUC_SELF_CFG_REQUEST_MSG_LEN (GUC_HXG_REQUEST_MSG_MIN_LEN + 3u)
5252
#define HOST2GUC_SELF_CFG_REQUEST_MSG_0_MBZ GUC_HXG_REQUEST_MSG_0_DATA0
53-
#define HOST2GUC_SELF_CFG_REQUEST_MSG_1_KLV_KEY (0xffff << 16)
54-
#define HOST2GUC_SELF_CFG_REQUEST_MSG_1_KLV_LEN (0xffff << 0)
53+
#define HOST2GUC_SELF_CFG_REQUEST_MSG_1_KLV_KEY (0xffffu << 16)
54+
#define HOST2GUC_SELF_CFG_REQUEST_MSG_1_KLV_LEN (0xffffu << 0)
5555
#define HOST2GUC_SELF_CFG_REQUEST_MSG_2_VALUE32 GUC_HXG_REQUEST_MSG_n_DATAn
5656
#define HOST2GUC_SELF_CFG_REQUEST_MSG_3_VALUE64 GUC_HXG_REQUEST_MSG_n_DATAn
5757

‎drivers/gpu/drm/xe/abi/guc_actions_slpc_abi.h‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -242,8 +242,8 @@ struct slpc_shared_data {
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(HOST2GUC_PC_SLPC_REQUEST_REQUEST_MSG_MIN_LEN + \
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HOST2GUC_PC_SLPC_EVENT_MAX_INPUT_ARGS)
244244
#define HOST2GUC_PC_SLPC_REQUEST_MSG_0_MBZ GUC_HXG_REQUEST_MSG_0_DATA0
245-
#define HOST2GUC_PC_SLPC_REQUEST_MSG_1_EVENT_ID (0xff << 8)
246-
#define HOST2GUC_PC_SLPC_REQUEST_MSG_1_EVENT_ARGC (0xff << 0)
245+
#define HOST2GUC_PC_SLPC_REQUEST_MSG_1_EVENT_ID (0xffu << 8)
246+
#define HOST2GUC_PC_SLPC_REQUEST_MSG_1_EVENT_ARGC (0xffu << 0)
247247
#define HOST2GUC_PC_SLPC_REQUEST_MSG_N_EVENT_DATA_N GUC_HXG_REQUEST_MSG_n_DATAn
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#endif

‎drivers/gpu/drm/xe/abi/guc_communication_ctb_abi.h‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -82,11 +82,11 @@ static_assert(sizeof(struct guc_ct_buffer_desc) == 64);
8282
#define GUC_CTB_HDR_LEN 1u
8383
#define GUC_CTB_MSG_MIN_LEN GUC_CTB_HDR_LEN
8484
#define GUC_CTB_MSG_MAX_LEN 256u
85-
#define GUC_CTB_MSG_0_FENCE (0xffff << 16)
86-
#define GUC_CTB_MSG_0_FORMAT (0xf << 12)
85+
#define GUC_CTB_MSG_0_FENCE (0xffffu << 16)
86+
#define GUC_CTB_MSG_0_FORMAT (0xfu << 12)
8787
#define GUC_CTB_FORMAT_HXG 0u
88-
#define GUC_CTB_MSG_0_RESERVED (0xf << 8)
89-
#define GUC_CTB_MSG_0_NUM_DWORDS (0xff << 0)
88+
#define GUC_CTB_MSG_0_RESERVED (0xfu << 8)
89+
#define GUC_CTB_MSG_0_NUM_DWORDS (0xffu << 0)
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/**
9292
* DOC: CTB HXG Message

‎drivers/gpu/drm/xe/abi/guc_klvs_abi.h‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -31,9 +31,9 @@
3131
*/
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3333
#define GUC_KLV_LEN_MIN 1u
34-
#define GUC_KLV_0_KEY (0xffff << 16)
35-
#define GUC_KLV_0_LEN (0xffff << 0)
36-
#define GUC_KLV_n_VALUE (0xffffffff << 0)
34+
#define GUC_KLV_0_KEY (0xffffu << 16)
35+
#define GUC_KLV_0_LEN (0xffffu << 0)
36+
#define GUC_KLV_n_VALUE (0xffffffffu << 0)
3737

3838
/**
3939
* DOC: GuC Self Config KLVs

‎drivers/gpu/drm/xe/abi/guc_messages_abi.h‎

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -40,18 +40,18 @@
4040
*/
4141

4242
#define GUC_HXG_MSG_MIN_LEN 1u
43-
#define GUC_HXG_MSG_0_ORIGIN (0x1 << 31)
43+
#define GUC_HXG_MSG_0_ORIGIN (0x1u << 31)
4444
#define GUC_HXG_ORIGIN_HOST 0u
4545
#define GUC_HXG_ORIGIN_GUC 1u
46-
#define GUC_HXG_MSG_0_TYPE (0x7 << 28)
46+
#define GUC_HXG_MSG_0_TYPE (0x7u << 28)
4747
#define GUC_HXG_TYPE_REQUEST 0u
4848
#define GUC_HXG_TYPE_EVENT 1u
4949
#define GUC_HXG_TYPE_NO_RESPONSE_BUSY 3u
5050
#define GUC_HXG_TYPE_NO_RESPONSE_RETRY 5u
5151
#define GUC_HXG_TYPE_RESPONSE_FAILURE 6u
5252
#define GUC_HXG_TYPE_RESPONSE_SUCCESS 7u
53-
#define GUC_HXG_MSG_0_AUX (0xfffffff << 0)
54-
#define GUC_HXG_MSG_n_PAYLOAD (0xffffffff << 0)
53+
#define GUC_HXG_MSG_0_AUX (0xfffffffu << 0)
54+
#define GUC_HXG_MSG_n_PAYLOAD (0xffffffffu << 0)
5555

5656
/**
5757
* DOC: HXG Request
@@ -85,8 +85,8 @@
8585
*/
8686

8787
#define GUC_HXG_REQUEST_MSG_MIN_LEN GUC_HXG_MSG_MIN_LEN
88-
#define GUC_HXG_REQUEST_MSG_0_DATA0 (0xfff << 16)
89-
#define GUC_HXG_REQUEST_MSG_0_ACTION (0xffff << 0)
88+
#define GUC_HXG_REQUEST_MSG_0_DATA0 (0xfffu << 16)
89+
#define GUC_HXG_REQUEST_MSG_0_ACTION (0xffffu << 0)
9090
#define GUC_HXG_REQUEST_MSG_n_DATAn GUC_HXG_MSG_n_PAYLOAD
9191

9292
/**
@@ -117,8 +117,8 @@
117117
*/
118118

119119
#define GUC_HXG_EVENT_MSG_MIN_LEN GUC_HXG_MSG_MIN_LEN
120-
#define GUC_HXG_EVENT_MSG_0_DATA0 (0xfff << 16)
121-
#define GUC_HXG_EVENT_MSG_0_ACTION (0xffff << 0)
120+
#define GUC_HXG_EVENT_MSG_0_DATA0 (0xfffu << 16)
121+
#define GUC_HXG_EVENT_MSG_0_ACTION (0xffffu << 0)
122122
#define GUC_HXG_EVENT_MSG_n_DATAn GUC_HXG_MSG_n_PAYLOAD
123123

124124
/**
@@ -188,8 +188,8 @@
188188
*/
189189

190190
#define GUC_HXG_FAILURE_MSG_LEN GUC_HXG_MSG_MIN_LEN
191-
#define GUC_HXG_FAILURE_MSG_0_HINT (0xfff << 16)
192-
#define GUC_HXG_FAILURE_MSG_0_ERROR (0xffff << 0)
191+
#define GUC_HXG_FAILURE_MSG_0_HINT (0xfffu << 16)
192+
#define GUC_HXG_FAILURE_MSG_0_ERROR (0xffffu << 0)
193193

194194
/**
195195
* DOC: HXG Response

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