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Aidan MacDonaldbebarino
Aidan MacDonald
authored and
bebarino
committed
clk: ingenic: Mark critical clocks in Ingenic SoCs
Consider CPU, L2 cache, and memory clocks as critical to prevent them -- and the parent clocks -- from being automatically gated, since nothing calls clk_get() on these clocks. Gating the CPU clock hangs the processor, and gating memory makes external DRAM inaccessible. Normal kernel code can't hope to deal with either situation so those clocks have to be critical. The L2 cache is required only if caches are running, and could be gated if the kernel takes care to flush and disable caches before gating the clock. There's no mechanism to do this, and probably no reason to do it, so it's simpler to mark the L2 cache as critical. Signed-off-by: Aidan MacDonald <aidanmacdonald.0x0@gmail.com> Reviewed-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20220428164454.17908-3-aidanmacdonald.0x0@gmail.com Tested-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> # On X1000 and X1830 Signed-off-by: Stephen Boyd <sboyd@kernel.org>
1 parent bacf743 commit ca54d06

7 files changed

Lines changed: 76 additions & 0 deletions

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‎drivers/clk/ingenic/jz4725b-cgu.c‎

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -87,6 +87,11 @@ static const struct ingenic_cgu_clk_info jz4725b_cgu_clocks[] = {
8787

8888
[JZ4725B_CLK_CCLK] = {
8989
"cclk", CGU_CLK_DIV,
90+
/*
91+
* Disabling the CPU clock or any parent clocks will hang the
92+
* system; mark it critical.
93+
*/
94+
.flags = CLK_IS_CRITICAL,
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.parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
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.div = {
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CGU_REG_CPCCR, 0, 1, 4, 22, -1, -1, 0,
@@ -114,6 +119,11 @@ static const struct ingenic_cgu_clk_info jz4725b_cgu_clocks[] = {
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115120
[JZ4725B_CLK_MCLK] = {
116121
"mclk", CGU_CLK_DIV,
122+
/*
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* Disabling MCLK or its parents will render DRAM
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* inaccessible; mark it critical.
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*/
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.flags = CLK_IS_CRITICAL,
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.parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
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.div = {
119129
CGU_REG_CPCCR, 12, 1, 4, 22, -1, -1, 0,

‎drivers/clk/ingenic/jz4740-cgu.c‎

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -102,6 +102,11 @@ static const struct ingenic_cgu_clk_info jz4740_cgu_clocks[] = {
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[JZ4740_CLK_CCLK] = {
104104
"cclk", CGU_CLK_DIV,
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/*
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* Disabling the CPU clock or any parent clocks will hang the
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* system; mark it critical.
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*/
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.flags = CLK_IS_CRITICAL,
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.parents = { JZ4740_CLK_PLL, -1, -1, -1 },
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.div = {
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CGU_REG_CPCCR, 0, 1, 4, 22, -1, -1, 0,
@@ -129,6 +134,11 @@ static const struct ingenic_cgu_clk_info jz4740_cgu_clocks[] = {
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130135
[JZ4740_CLK_MCLK] = {
131136
"mclk", CGU_CLK_DIV,
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/*
138+
* Disabling MCLK or its parents will render DRAM
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* inaccessible; mark it critical.
140+
*/
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.flags = CLK_IS_CRITICAL,
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.parents = { JZ4740_CLK_PLL, -1, -1, -1 },
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.div = {
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CGU_REG_CPCCR, 12, 1, 4, 22, -1, -1, 0,

‎drivers/clk/ingenic/jz4760-cgu.c‎

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -143,6 +143,11 @@ static const struct ingenic_cgu_clk_info jz4760_cgu_clocks[] = {
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[JZ4760_CLK_CCLK] = {
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"cclk", CGU_CLK_DIV,
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/*
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* Disabling the CPU clock or any parent clocks will hang the
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* system; mark it critical.
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*/
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.flags = CLK_IS_CRITICAL,
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.parents = { JZ4760_CLK_PLL0, },
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.div = {
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CGU_REG_CPCCR, 0, 1, 4, 22, -1, -1, 0,
@@ -175,6 +180,11 @@ static const struct ingenic_cgu_clk_info jz4760_cgu_clocks[] = {
175180
},
176181
[JZ4760_CLK_MCLK] = {
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"mclk", CGU_CLK_DIV,
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/*
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* Disabling MCLK or its parents will render DRAM
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* inaccessible; mark it critical.
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*/
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.flags = CLK_IS_CRITICAL,
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.parents = { JZ4760_CLK_PLL0, },
179189
.div = {
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CGU_REG_CPCCR, 12, 1, 4, 22, -1, -1, 0,

‎drivers/clk/ingenic/jz4770-cgu.c‎

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Original file line numberDiff line numberDiff line change
@@ -149,6 +149,11 @@ static const struct ingenic_cgu_clk_info jz4770_cgu_clocks[] = {
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150150
[JZ4770_CLK_CCLK] = {
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"cclk", CGU_CLK_DIV,
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/*
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* Disabling the CPU clock or any parent clocks will hang the
154+
* system; mark it critical.
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*/
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.flags = CLK_IS_CRITICAL,
152157
.parents = { JZ4770_CLK_PLL0, },
153158
.div = {
154159
CGU_REG_CPCCR, 0, 1, 4, 22, -1, -1, 0,

‎drivers/clk/ingenic/jz4780-cgu.c‎

Lines changed: 15 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -341,12 +341,22 @@ static const struct ingenic_cgu_clk_info jz4780_cgu_clocks[] = {
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342342
[JZ4780_CLK_CPU] = {
343343
"cpu", CGU_CLK_DIV,
344+
/*
345+
* Disabling the CPU clock or any parent clocks will hang the
346+
* system; mark it critical.
347+
*/
348+
.flags = CLK_IS_CRITICAL,
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.parents = { JZ4780_CLK_CPUMUX, -1, -1, -1 },
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.div = { CGU_REG_CLOCKCONTROL, 0, 1, 4, 22, -1, -1 },
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},
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348353
[JZ4780_CLK_L2CACHE] = {
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"l2cache", CGU_CLK_DIV,
355+
/*
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* The L2 cache clock is critical if caches are enabled and
357+
* disabling it or any parent clocks will hang the system.
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*/
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.flags = CLK_IS_CRITICAL,
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.parents = { JZ4780_CLK_CPUMUX, -1, -1, -1 },
351361
.div = { CGU_REG_CLOCKCONTROL, 4, 1, 4, -1, -1, -1 },
352362
},
@@ -380,6 +390,11 @@ static const struct ingenic_cgu_clk_info jz4780_cgu_clocks[] = {
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381391
[JZ4780_CLK_DDR] = {
382392
"ddr", CGU_CLK_MUX | CGU_CLK_DIV,
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/*
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* Disabling DDR clock or its parents will render DRAM
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* inaccessible; mark it critical.
396+
*/
397+
.flags = CLK_IS_CRITICAL,
383398
.parents = { -1, JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, -1 },
384399
.mux = { CGU_REG_DDRCDR, 30, 2 },
385400
.div = { CGU_REG_DDRCDR, 0, 1, 4, 29, 28, 27 },

‎drivers/clk/ingenic/x1000-cgu.c‎

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Original file line numberDiff line numberDiff line change
@@ -251,13 +251,23 @@ static const struct ingenic_cgu_clk_info x1000_cgu_clocks[] = {
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252252
[X1000_CLK_CPU] = {
253253
"cpu", CGU_CLK_DIV | CGU_CLK_GATE,
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/*
255+
* Disabling the CPU clock or any parent clocks will hang the
256+
* system; mark it critical.
257+
*/
258+
.flags = CLK_IS_CRITICAL,
254259
.parents = { X1000_CLK_CPUMUX, -1, -1, -1 },
255260
.div = { CGU_REG_CPCCR, 0, 1, 4, 22, -1, -1 },
256261
.gate = { CGU_REG_CLKGR, 30 },
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},
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259264
[X1000_CLK_L2CACHE] = {
260265
"l2cache", CGU_CLK_DIV,
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/*
267+
* The L2 cache clock is critical if caches are enabled and
268+
* disabling it or any parent clocks will hang the system.
269+
*/
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.flags = CLK_IS_CRITICAL,
261271
.parents = { X1000_CLK_CPUMUX, -1, -1, -1 },
262272
.div = { CGU_REG_CPCCR, 4, 1, 4, 22, -1, -1 },
263273
},
@@ -290,6 +300,11 @@ static const struct ingenic_cgu_clk_info x1000_cgu_clocks[] = {
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291301
[X1000_CLK_DDR] = {
292302
"ddr", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
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/*
304+
* Disabling DDR clock or its parents will render DRAM
305+
* inaccessible; mark it critical.
306+
*/
307+
.flags = CLK_IS_CRITICAL,
293308
.parents = { -1, X1000_CLK_SCLKA, X1000_CLK_MPLL, -1 },
294309
.mux = { CGU_REG_DDRCDR, 30, 2 },
295310
.div = { CGU_REG_DDRCDR, 0, 1, 4, 29, 28, 27 },

‎drivers/clk/ingenic/x1830-cgu.c‎

Lines changed: 11 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -225,13 +225,19 @@ static const struct ingenic_cgu_clk_info x1830_cgu_clocks[] = {
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226226
[X1830_CLK_CPU] = {
227227
"cpu", CGU_CLK_DIV | CGU_CLK_GATE,
228+
.flags = CLK_IS_CRITICAL,
228229
.parents = { X1830_CLK_CPUMUX, -1, -1, -1 },
229230
.div = { CGU_REG_CPCCR, 0, 1, 4, 22, -1, -1 },
230231
.gate = { CGU_REG_CLKGR1, 15 },
231232
},
232233

233234
[X1830_CLK_L2CACHE] = {
234235
"l2cache", CGU_CLK_DIV,
236+
/*
237+
* The L2 cache clock is critical if caches are enabled and
238+
* disabling it or any parent clocks will hang the system.
239+
*/
240+
.flags = CLK_IS_CRITICAL,
235241
.parents = { X1830_CLK_CPUMUX, -1, -1, -1 },
236242
.div = { CGU_REG_CPCCR, 4, 1, 4, 22, -1, -1 },
237243
},
@@ -264,6 +270,11 @@ static const struct ingenic_cgu_clk_info x1830_cgu_clocks[] = {
264270

265271
[X1830_CLK_DDR] = {
266272
"ddr", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
273+
/*
274+
* Disabling DDR clock or its parents will render DRAM
275+
* inaccessible; mark it critical.
276+
*/
277+
.flags = CLK_IS_CRITICAL,
267278
.parents = { -1, X1830_CLK_SCLKA, X1830_CLK_MPLL, -1 },
268279
.mux = { CGU_REG_DDRCDR, 30, 2 },
269280
.div = { CGU_REG_DDRCDR, 0, 1, 4, 29, 28, 27 },

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