KVM: x86: Drop ASSERT() on I/O APIC EOIs being only for LEVEL_to WARN_ON_ONCE

Remove kvm_ioapic_update_eoi_one()'s ASSERT() that the vector's entry is
configured to be level-triggered, as KVM intercepts and forward EOIs to
the I/O APIC even for edge-triggered IRQs (see kvm_ioapic_scan_entry()),
and nothing guarantees the local APIC's TMR register is synchronized with
the I/O APIC redirection table, i.e. the @trigger_mode check just out of
sight doesn't provide any meaningful protection.

Given that roughly half of the historic ASSERT()s are/were guest- and/or
user-triggerable, it's safe to assume no one has run meaningful workloads
with DEBUG=1, i.e. that the ASSERT() has been dead code since it was
added 18+ years ago.

Opportunistically drop the unnecessary forward declaration of
kvm_ioapic_update_eoi_one().

For all intents and purposes, no functional change intended.

Link: https://patch.msgid.link/20251206004311.479939-4-seanjc@google.com
Signed-off-by: Sean Christopherson <seanjc@google.com>

Author: sean-jc

arch/x86/kvm/ioapic.c

@@ -37,11 +37,6 @@
 static int ioapic_service(struct kvm_ioapic *vioapic, int irq,
 		bool line_status);
 
-static void kvm_ioapic_update_eoi_one(struct kvm_vcpu *vcpu,
-				      struct kvm_ioapic *ioapic,
-				      int trigger_mode,
-				      int pin);
-
 static unsigned long ioapic_read_indirect(struct kvm_ioapic *ioapic)
 {
 	unsigned long result = 0;
@@ -564,7 +559,6 @@ static void kvm_ioapic_update_eoi_one(struct kvm_vcpu *vcpu,
 	    kvm_lapic_get_reg(apic, APIC_SPIV) & APIC_SPIV_DIRECTED_EOI)
 		return;
 
-	ASSERT(ent->fields.trig_mode == IOAPIC_LEVEL_TRIG);
 	ent->fields.remote_irr = 0;
 	if (!ent->fields.mask && (ioapic->irr & (1 << pin))) {
 		++ioapic->irq_eoi[pin];