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airliedairlied
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Merge tag 'drm-intel-gt-next-2023-09-28' of git://anongit.freedesktop.org/drm/drm-intel into drm-next
Driver Changes: Fixes/improvements/new stuff: - Fix TLB-Invalidation seqno store [mtl] (Alan Previn) - Force a reset on internal GuC error [guc] (John Harrison) - Define GSC fw [gsc] (Daniele Ceraolo Spurio) - Update workaround 14016712196 [dg2/mtl] (Tejas Upadhyay) - Mark requests for GuC virtual engines to avoid use-after-free (Andrzej Hajda) - Add Wa_14015150844 [dg2/mtl] (Shekhar Chauhan) - Prevent error pointer dereference (Dan Carpenter) - Add Wa_18022495364 [tgl,adl,rpl] (Dnyaneshwar Bhadane) - Fix GuC PMU by moving execlist stats initialization to execlist specific setup (Umesh Nerlige Ramappa) - Fix PXP firmware load [pxp/mtl] (Alan Previn) - Fix execution/context state of PXP contexts (Alan Previn) - Limit the length of an sg list to the requested length (Matthew Wilcox) - Fix reservation address in ggtt_reserve_guc_top [guc] (Javier Pello) - Add Wa_18028616096 [dg2] (Shekhar Chauhan) - Get runtime pm in busyness worker only if already active [guc/pmu] (Umesh Nerlige Ramappa) - Don't set PIPE_CONTROL_FLUSH_L3 for aux inval (Nirmoy Das) Future platform enablement: - Fix and consolidate some workaround checks, make others IP version based [mtl] (Matt Roper) - Replace Meteorlake subplatforms with IP version checks (Matt Roper) - Adding DeviceID for Arrowlake-S under MTL [mtl] (Nemesa Garg) - Run relevant bits of debugfs drop_caches per GT (Tvrtko Ursulin) Miscellaneous: - Remove Wa_15010599737 [dg2] (Shekhar Chauhan) - Align igt_spinner_create_request with hangcheck [selftests] (Jonathan Cavitt) - Remove pre-production workarounds [dg2] (Matt Roper) - Tidy some workaround definitions (Matt Roper) - Wait longer for tasks in migrate selftest [gt] (Jonathan Cavitt) - Skip WA verification for GEN7_MISCCPCTL on DG2 [gt] (Andrzej Hajda) - Silence injected failure in the load via GSC path [huc] (Daniele Ceraolo Spurio) - Refactor deprecated strncpy (Justin Stitt) - Update RC6 mask for mtl_drpc [debugfs/mtl] (Badal Nilawar) - Remove a static inline that requires including i915_drv.h [gt] (Jani Nikula) - Remove inlines from i915_gem_execbuffer.c [gem] (Jani Nikula) - Remove gtt_offset from stream->oa_buffer.head/.tail [perf] (Ashutosh Dixit) - Do not disable preemption for resets (Tvrtko Ursulin) Signed-off-by: Dave Airlie <airlied@redhat.com> From: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/ZRVzL02VFuwIkcGl@tursulin-desk
2 parents 79fb229 + 03d6814 commit caacbdc

46 files changed

Lines changed: 522 additions & 702 deletions

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‎drivers/gpu/drm/i915/display/skl_universal_plane.c‎

Lines changed: 1 addition & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -20,6 +20,7 @@
2020
#include "skl_scaler.h"
2121
#include "skl_universal_plane.h"
2222
#include "skl_watermark.h"
23+
#include "gt/intel_gt.h"
2324
#include "pxp/intel_pxp.h"
2425

2526
static const u32 skl_plane_formats[] = {
@@ -2168,11 +2169,6 @@ skl_plane_disable_flip_done(struct intel_plane *plane)
21682169
static bool skl_plane_has_rc_ccs(struct drm_i915_private *i915,
21692170
enum pipe pipe, enum plane_id plane_id)
21702171
{
2171-
/* Wa_14017240301 */
2172-
if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
2173-
IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
2174-
return false;
2175-
21762172
/* Wa_22011186057 */
21772173
if (IS_ALDERLAKE_P(i915) && IS_DISPLAY_STEP(i915, STEP_A0, STEP_B0))
21782174
return false;

‎drivers/gpu/drm/i915/gem/i915_gem_create.c‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -405,8 +405,8 @@ static int ext_set_pat(struct i915_user_extension __user *base, void *data)
405405
BUILD_BUG_ON(sizeof(struct drm_i915_gem_create_ext_set_pat) !=
406406
offsetofend(struct drm_i915_gem_create_ext_set_pat, rsvd));
407407

408-
/* Limiting the extension only to Meteor Lake */
409-
if (!IS_METEORLAKE(i915))
408+
/* Limiting the extension only to Xe_LPG and beyond */
409+
if (GRAPHICS_VER_FULL(i915) < IP_VER(12, 70))
410410
return -ENODEV;
411411

412412
if (copy_from_user(&ext, base, sizeof(ext)))

‎drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c‎

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -321,7 +321,7 @@ static int eb_pin_engine(struct i915_execbuffer *eb, bool throttle);
321321
static void eb_unpin_engine(struct i915_execbuffer *eb);
322322
static void eb_capture_release(struct i915_execbuffer *eb);
323323

324-
static inline bool eb_use_cmdparser(const struct i915_execbuffer *eb)
324+
static bool eb_use_cmdparser(const struct i915_execbuffer *eb)
325325
{
326326
return intel_engine_requires_cmd_parser(eb->context->engine) ||
327327
(intel_engine_using_cmd_parser(eb->context->engine) &&
@@ -433,7 +433,7 @@ static u64 eb_pin_flags(const struct drm_i915_gem_exec_object2 *entry,
433433
return pin_flags;
434434
}
435435

436-
static inline int
436+
static int
437437
eb_pin_vma(struct i915_execbuffer *eb,
438438
const struct drm_i915_gem_exec_object2 *entry,
439439
struct eb_vma *ev)
@@ -486,7 +486,7 @@ eb_pin_vma(struct i915_execbuffer *eb,
486486
return 0;
487487
}
488488

489-
static inline void
489+
static void
490490
eb_unreserve_vma(struct eb_vma *ev)
491491
{
492492
if (unlikely(ev->flags & __EXEC_OBJECT_HAS_FENCE))
@@ -548,7 +548,7 @@ eb_validate_vma(struct i915_execbuffer *eb,
548548
return 0;
549549
}
550550

551-
static inline bool
551+
static bool
552552
is_batch_buffer(struct i915_execbuffer *eb, unsigned int buffer_idx)
553553
{
554554
return eb->args->flags & I915_EXEC_BATCH_FIRST ?
@@ -628,8 +628,8 @@ eb_add_vma(struct i915_execbuffer *eb,
628628
return 0;
629629
}
630630

631-
static inline int use_cpu_reloc(const struct reloc_cache *cache,
632-
const struct drm_i915_gem_object *obj)
631+
static int use_cpu_reloc(const struct reloc_cache *cache,
632+
const struct drm_i915_gem_object *obj)
633633
{
634634
if (!i915_gem_object_has_struct_page(obj))
635635
return false;
@@ -1107,7 +1107,7 @@ static void eb_destroy(const struct i915_execbuffer *eb)
11071107
kfree(eb->buckets);
11081108
}
11091109

1110-
static inline u64
1110+
static u64
11111111
relocation_target(const struct drm_i915_gem_relocation_entry *reloc,
11121112
const struct i915_vma *target)
11131113
{
@@ -1128,19 +1128,19 @@ static void reloc_cache_init(struct reloc_cache *cache,
11281128
cache->node.flags = 0;
11291129
}
11301130

1131-
static inline void *unmask_page(unsigned long p)
1131+
static void *unmask_page(unsigned long p)
11321132
{
11331133
return (void *)(uintptr_t)(p & PAGE_MASK);
11341134
}
11351135

1136-
static inline unsigned int unmask_flags(unsigned long p)
1136+
static unsigned int unmask_flags(unsigned long p)
11371137
{
11381138
return p & ~PAGE_MASK;
11391139
}
11401140

11411141
#define KMAP 0x4 /* after CLFLUSH_FLAGS */
11421142

1143-
static inline struct i915_ggtt *cache_to_ggtt(struct reloc_cache *cache)
1143+
static struct i915_ggtt *cache_to_ggtt(struct reloc_cache *cache)
11441144
{
11451145
struct drm_i915_private *i915 =
11461146
container_of(cache, struct i915_execbuffer, reloc_cache)->i915;

‎drivers/gpu/drm/i915/gem/i915_gem_shmem.c‎

Lines changed: 7 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -100,6 +100,7 @@ int shmem_sg_alloc_table(struct drm_i915_private *i915, struct sg_table *st,
100100
st->nents = 0;
101101
for (i = 0; i < page_count; i++) {
102102
struct folio *folio;
103+
unsigned long nr_pages;
103104
const unsigned int shrink[] = {
104105
I915_SHRINK_BOUND | I915_SHRINK_UNBOUND,
105106
0,
@@ -150,20 +151,22 @@ int shmem_sg_alloc_table(struct drm_i915_private *i915, struct sg_table *st,
150151
}
151152
} while (1);
152153

154+
nr_pages = min_t(unsigned long,
155+
folio_nr_pages(folio), page_count - i);
153156
if (!i ||
154157
sg->length >= max_segment ||
155158
folio_pfn(folio) != next_pfn) {
156159
if (i)
157160
sg = sg_next(sg);
158161

159162
st->nents++;
160-
sg_set_folio(sg, folio, folio_size(folio), 0);
163+
sg_set_folio(sg, folio, nr_pages * PAGE_SIZE, 0);
161164
} else {
162165
/* XXX: could overflow? */
163-
sg->length += folio_size(folio);
166+
sg->length += nr_pages * PAGE_SIZE;
164167
}
165-
next_pfn = folio_pfn(folio) + folio_nr_pages(folio);
166-
i += folio_nr_pages(folio) - 1;
168+
next_pfn = folio_pfn(folio) + nr_pages;
169+
i += nr_pages - 1;
167170

168171
/* Check that the i965g/gm workaround works. */
169172
GEM_BUG_ON(gfp & __GFP_DMA32 && next_pfn >= 0x00100000UL);

‎drivers/gpu/drm/i915/gem/selftests/mock_context.c‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -36,7 +36,7 @@ mock_context(struct drm_i915_private *i915,
3636
if (name) {
3737
struct i915_ppgtt *ppgtt;
3838

39-
strncpy(ctx->name, name, sizeof(ctx->name) - 1);
39+
strscpy(ctx->name, name, sizeof(ctx->name));
4040

4141
ppgtt = mock_ppgtt(i915, name);
4242
if (!ppgtt)

‎drivers/gpu/drm/i915/gt/gen8_engine_cs.c‎

Lines changed: 15 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -4,9 +4,9 @@
44
*/
55

66
#include "gen8_engine_cs.h"
7-
#include "i915_drv.h"
87
#include "intel_engine_regs.h"
98
#include "intel_gpu_commands.h"
9+
#include "intel_gt.h"
1010
#include "intel_lrc.h"
1111
#include "intel_ring.h"
1212

@@ -226,8 +226,8 @@ u32 *gen12_emit_aux_table_inv(struct intel_engine_cs *engine, u32 *cs)
226226
static int mtl_dummy_pipe_control(struct i915_request *rq)
227227
{
228228
/* Wa_14016712196 */
229-
if (IS_MTL_GRAPHICS_STEP(rq->i915, M, STEP_A0, STEP_B0) ||
230-
IS_MTL_GRAPHICS_STEP(rq->i915, P, STEP_A0, STEP_B0)) {
229+
if (IS_GFX_GT_IP_RANGE(rq->engine->gt, IP_VER(12, 70), IP_VER(12, 71)) ||
230+
IS_DG2(rq->i915)) {
231231
u32 *cs;
232232

233233
/* dummy PIPE_CONTROL + depth flush */
@@ -271,8 +271,17 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode)
271271
if (GRAPHICS_VER_FULL(rq->i915) >= IP_VER(12, 70))
272272
bit_group_0 |= PIPE_CONTROL_CCS_FLUSH;
273273

274+
/*
275+
* L3 fabric flush is needed for AUX CCS invalidation
276+
* which happens as part of pipe-control so we can
277+
* ignore PIPE_CONTROL_FLUSH_L3. Also PIPE_CONTROL_FLUSH_L3
278+
* deals with Protected Memory which is not needed for
279+
* AUX CCS invalidation and lead to unwanted side effects.
280+
*/
281+
if (mode & EMIT_FLUSH)
282+
bit_group_1 |= PIPE_CONTROL_FLUSH_L3;
283+
274284
bit_group_1 |= PIPE_CONTROL_TILE_CACHE_FLUSH;
275-
bit_group_1 |= PIPE_CONTROL_FLUSH_L3;
276285
bit_group_1 |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
277286
bit_group_1 |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
278287
/* Wa_1409600907:tgl,adl-p */
@@ -799,6 +808,7 @@ u32 *gen12_emit_fini_breadcrumb_xcs(struct i915_request *rq, u32 *cs)
799808
u32 *gen12_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs)
800809
{
801810
struct drm_i915_private *i915 = rq->i915;
811+
struct intel_gt *gt = rq->engine->gt;
802812
u32 flags = (PIPE_CONTROL_CS_STALL |
803813
PIPE_CONTROL_TLB_INVALIDATE |
804814
PIPE_CONTROL_TILE_CACHE_FLUSH |
@@ -809,8 +819,7 @@ u32 *gen12_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs)
809819
PIPE_CONTROL_FLUSH_ENABLE);
810820

811821
/* Wa_14016712196 */
812-
if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
813-
IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
822+
if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 71)) || IS_DG2(i915))
814823
/* dummy PIPE_CONTROL + depth flush */
815824
cs = gen12_emit_pipe_control(cs, 0,
816825
PIPE_CONTROL_DEPTH_CACHE_FLUSH, 0);

‎drivers/gpu/drm/i915/gt/intel_engine_cs.c‎

Lines changed: 1 addition & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -558,7 +558,6 @@ static int intel_engine_setup(struct intel_gt *gt, enum intel_engine_id id,
558558
DRIVER_CAPS(i915)->has_logical_contexts = true;
559559

560560
ewma__engine_latency_init(&engine->latency);
561-
seqcount_init(&engine->stats.execlists.lock);
562561

563562
ATOMIC_INIT_NOTIFIER_HEAD(&engine->context_status_notifier);
564563

@@ -1617,9 +1616,7 @@ static int __intel_engine_stop_cs(struct intel_engine_cs *engine,
16171616
* Wa_22011802037: Prior to doing a reset, ensure CS is
16181617
* stopped, set ring stop bit and prefetch disable bit to halt CS
16191618
*/
1620-
if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
1621-
(GRAPHICS_VER(engine->i915) >= 11 &&
1622-
GRAPHICS_VER_FULL(engine->i915) < IP_VER(12, 70)))
1619+
if (intel_engine_reset_needs_wa_22011802037(engine->gt))
16231620
intel_uncore_write_fw(uncore, RING_MODE_GEN7(engine->mmio_base),
16241621
_MASKED_BIT_ENABLE(GEN12_GFX_PREFETCH_DISABLE));
16251622

‎drivers/gpu/drm/i915/gt/intel_engine_pm.c‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -21,7 +21,7 @@ static void intel_gsc_idle_msg_enable(struct intel_engine_cs *engine)
2121
{
2222
struct drm_i915_private *i915 = engine->i915;
2323

24-
if (IS_METEORLAKE(i915) && engine->id == GSC0) {
24+
if (MEDIA_VER(i915) >= 13 && engine->id == GSC0) {
2525
intel_uncore_write(engine->gt->uncore,
2626
RC_PSMI_CTRL_GSCCS,
2727
_MASKED_BIT_DISABLE(IDLE_MSG_DISABLE));

‎drivers/gpu/drm/i915/gt/intel_engine_regs.h‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -177,6 +177,7 @@
177177
#define CTX_CTRL_RS_CTX_ENABLE REG_BIT(1)
178178
#define CTX_CTRL_ENGINE_CTX_SAVE_INHIBIT REG_BIT(2)
179179
#define CTX_CTRL_INHIBIT_SYN_CTX_SWITCH REG_BIT(3)
180+
#define GEN12_CTX_CTRL_RUNALONE_MODE REG_BIT(7)
180181
#define GEN12_CTX_CTRL_OAR_CONTEXT_ENABLE REG_BIT(8)
181182
#define RING_CTX_SR_CTL(base) _MMIO((base) + 0x244)
182183
#define RING_SEMA_WAIT_POLL(base) _MMIO((base) + 0x24c)

‎drivers/gpu/drm/i915/gt/intel_execlists_submission.c‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -3001,9 +3001,7 @@ static void execlists_reset_prepare(struct intel_engine_cs *engine)
30013001
* Wa_22011802037: In addition to stopping the cs, we need
30023002
* to wait for any pending mi force wakeups
30033003
*/
3004-
if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
3005-
(GRAPHICS_VER(engine->i915) >= 11 &&
3006-
GRAPHICS_VER_FULL(engine->i915) < IP_VER(12, 70)))
3004+
if (intel_engine_reset_needs_wa_22011802037(engine->gt))
30073005
intel_engine_wait_for_pending_mi_fw(engine);
30083006

30093007
engine->execlists.reset_ccid = active_ccid(engine);
@@ -3550,6 +3548,8 @@ int intel_execlists_submission_setup(struct intel_engine_cs *engine)
35503548
logical_ring_default_vfuncs(engine);
35513549
logical_ring_default_irqs(engine);
35523550

3551+
seqcount_init(&engine->stats.execlists.lock);
3552+
35533553
if (engine->flags & I915_ENGINE_HAS_RCS_REG_STATE)
35543554
rcs_submission_override(engine);
35553555

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