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ukleinekhdeller
ukleinek
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fbdev: au1100fb: Fold au1100fb.h into its only user
This gets rid of a header that is only used once. The copyrights and license specifications are all already covered in the au1100fb.c file. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@baylibre.com> Signed-off-by: Helge Deller <deller@gmx.de>
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‎drivers/video/fbdev/au1100fb.c‎

Lines changed: 338 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -60,7 +60,344 @@
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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63-
#include "au1100fb.h"
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#if defined(__BIG_ENDIAN)
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#define LCD_CONTROL_DEFAULT_PO LCD_CONTROL_PO_11
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#else
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#define LCD_CONTROL_DEFAULT_PO LCD_CONTROL_PO_00
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#endif
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#define LCD_CONTROL_DEFAULT_SBPPF LCD_CONTROL_SBPPF_565
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/********************************************************************/
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/* LCD controller restrictions */
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#define AU1100_LCD_MAX_XRES 800
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#define AU1100_LCD_MAX_YRES 600
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#define AU1100_LCD_MAX_BPP 16
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#define AU1100_LCD_MAX_CLK 48000000
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#define AU1100_LCD_NBR_PALETTE_ENTRIES 256
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/* Default number of visible screen buffer to allocate */
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#define AU1100FB_NBR_VIDEO_BUFFERS 4
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/********************************************************************/
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struct au1100fb_panel
85+
{
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const char name[25]; /* Full name <vendor>_<model> */
87+
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u32 control_base; /* Mode-independent control values */
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u32 clkcontrol_base; /* Panel pixclock preferences */
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u32 horztiming;
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u32 verttiming;
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u32 xres; /* Maximum horizontal resolution */
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u32 yres; /* Maximum vertical resolution */
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u32 bpp; /* Maximum depth supported */
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};
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struct au1100fb_regs
100+
{
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u32 lcd_control;
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u32 lcd_intstatus;
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u32 lcd_intenable;
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u32 lcd_horztiming;
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u32 lcd_verttiming;
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u32 lcd_clkcontrol;
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u32 lcd_dmaaddr0;
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u32 lcd_dmaaddr1;
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u32 lcd_words;
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u32 lcd_pwmdiv;
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u32 lcd_pwmhi;
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u32 reserved[(0x0400-0x002C)/4];
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u32 lcd_palettebase[256];
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};
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struct au1100fb_device {
117+
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struct fb_info info; /* FB driver info record */
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struct au1100fb_panel *panel; /* Panel connected to this device */
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struct au1100fb_regs* regs; /* Registers memory map */
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size_t regs_len;
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unsigned int regs_phys;
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#ifdef CONFIG_PM
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/* stores the register values during suspend */
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struct au1100fb_regs pm_regs;
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#endif
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unsigned char* fb_mem; /* FrameBuffer memory map */
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size_t fb_len;
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dma_addr_t fb_phys;
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int panel_idx;
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struct clk *lcdclk;
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struct device *dev;
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};
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/********************************************************************/
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#define LCD_CONTROL (AU1100_LCD_BASE + 0x0)
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#define LCD_CONTROL_SBB_BIT 21
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#define LCD_CONTROL_SBB_MASK (0x3 << LCD_CONTROL_SBB_BIT)
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#define LCD_CONTROL_SBB_1 (0 << LCD_CONTROL_SBB_BIT)
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#define LCD_CONTROL_SBB_2 (1 << LCD_CONTROL_SBB_BIT)
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#define LCD_CONTROL_SBB_3 (2 << LCD_CONTROL_SBB_BIT)
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#define LCD_CONTROL_SBB_4 (3 << LCD_CONTROL_SBB_BIT)
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#define LCD_CONTROL_SBPPF_BIT 18
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#define LCD_CONTROL_SBPPF_MASK (0x7 << LCD_CONTROL_SBPPF_BIT)
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#define LCD_CONTROL_SBPPF_655 (0 << LCD_CONTROL_SBPPF_BIT)
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#define LCD_CONTROL_SBPPF_565 (1 << LCD_CONTROL_SBPPF_BIT)
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#define LCD_CONTROL_SBPPF_556 (2 << LCD_CONTROL_SBPPF_BIT)
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#define LCD_CONTROL_SBPPF_1555 (3 << LCD_CONTROL_SBPPF_BIT)
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#define LCD_CONTROL_SBPPF_5551 (4 << LCD_CONTROL_SBPPF_BIT)
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#define LCD_CONTROL_WP (1<<17)
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#define LCD_CONTROL_WD (1<<16)
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#define LCD_CONTROL_C (1<<15)
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#define LCD_CONTROL_SM_BIT 13
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#define LCD_CONTROL_SM_MASK (0x3 << LCD_CONTROL_SM_BIT)
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#define LCD_CONTROL_SM_0 (0 << LCD_CONTROL_SM_BIT)
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#define LCD_CONTROL_SM_90 (1 << LCD_CONTROL_SM_BIT)
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#define LCD_CONTROL_SM_180 (2 << LCD_CONTROL_SM_BIT)
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#define LCD_CONTROL_SM_270 (3 << LCD_CONTROL_SM_BIT)
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#define LCD_CONTROL_DB (1<<12)
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#define LCD_CONTROL_CCO (1<<11)
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#define LCD_CONTROL_DP (1<<10)
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#define LCD_CONTROL_PO_BIT 8
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#define LCD_CONTROL_PO_MASK (0x3 << LCD_CONTROL_PO_BIT)
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#define LCD_CONTROL_PO_00 (0 << LCD_CONTROL_PO_BIT)
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#define LCD_CONTROL_PO_01 (1 << LCD_CONTROL_PO_BIT)
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#define LCD_CONTROL_PO_10 (2 << LCD_CONTROL_PO_BIT)
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#define LCD_CONTROL_PO_11 (3 << LCD_CONTROL_PO_BIT)
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#define LCD_CONTROL_MPI (1<<7)
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#define LCD_CONTROL_PT (1<<6)
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#define LCD_CONTROL_PC (1<<5)
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#define LCD_CONTROL_BPP_BIT 1
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#define LCD_CONTROL_BPP_MASK (0x7 << LCD_CONTROL_BPP_BIT)
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#define LCD_CONTROL_BPP_1 (0 << LCD_CONTROL_BPP_BIT)
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#define LCD_CONTROL_BPP_2 (1 << LCD_CONTROL_BPP_BIT)
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#define LCD_CONTROL_BPP_4 (2 << LCD_CONTROL_BPP_BIT)
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#define LCD_CONTROL_BPP_8 (3 << LCD_CONTROL_BPP_BIT)
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#define LCD_CONTROL_BPP_12 (4 << LCD_CONTROL_BPP_BIT)
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#define LCD_CONTROL_BPP_16 (5 << LCD_CONTROL_BPP_BIT)
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#define LCD_CONTROL_GO (1<<0)
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#define LCD_INTSTATUS (AU1100_LCD_BASE + 0x4)
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#define LCD_INTENABLE (AU1100_LCD_BASE + 0x8)
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#define LCD_INT_SD (1<<7)
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#define LCD_INT_OF (1<<6)
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#define LCD_INT_UF (1<<5)
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#define LCD_INT_SA (1<<3)
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#define LCD_INT_SS (1<<2)
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#define LCD_INT_S1 (1<<1)
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#define LCD_INT_S0 (1<<0)
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#define LCD_HORZTIMING (AU1100_LCD_BASE + 0xC)
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#define LCD_HORZTIMING_HN2_BIT 24
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#define LCD_HORZTIMING_HN2_MASK (0xFF << LCD_HORZTIMING_HN2_BIT)
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#define LCD_HORZTIMING_HN2_N(N) ((((N)-1) << LCD_HORZTIMING_HN2_BIT) & LCD_HORZTIMING_HN2_MASK)
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#define LCD_HORZTIMING_HN1_BIT 16
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#define LCD_HORZTIMING_HN1_MASK (0xFF << LCD_HORZTIMING_HN1_BIT)
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#define LCD_HORZTIMING_HN1_N(N) ((((N)-1) << LCD_HORZTIMING_HN1_BIT) & LCD_HORZTIMING_HN1_MASK)
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#define LCD_HORZTIMING_HPW_BIT 10
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#define LCD_HORZTIMING_HPW_MASK (0x3F << LCD_HORZTIMING_HPW_BIT)
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#define LCD_HORZTIMING_HPW_N(N) ((((N)-1) << LCD_HORZTIMING_HPW_BIT) & LCD_HORZTIMING_HPW_MASK)
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#define LCD_HORZTIMING_PPL_BIT 0
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#define LCD_HORZTIMING_PPL_MASK (0x3FF << LCD_HORZTIMING_PPL_BIT)
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#define LCD_HORZTIMING_PPL_N(N) ((((N)-1) << LCD_HORZTIMING_PPL_BIT) & LCD_HORZTIMING_PPL_MASK)
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#define LCD_VERTTIMING (AU1100_LCD_BASE + 0x10)
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#define LCD_VERTTIMING_VN2_BIT 24
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#define LCD_VERTTIMING_VN2_MASK (0xFF << LCD_VERTTIMING_VN2_BIT)
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#define LCD_VERTTIMING_VN2_N(N) ((((N)-1) << LCD_VERTTIMING_VN2_BIT) & LCD_VERTTIMING_VN2_MASK)
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#define LCD_VERTTIMING_VN1_BIT 16
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#define LCD_VERTTIMING_VN1_MASK (0xFF << LCD_VERTTIMING_VN1_BIT)
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#define LCD_VERTTIMING_VN1_N(N) ((((N)-1) << LCD_VERTTIMING_VN1_BIT) & LCD_VERTTIMING_VN1_MASK)
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#define LCD_VERTTIMING_VPW_BIT 10
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#define LCD_VERTTIMING_VPW_MASK (0x3F << LCD_VERTTIMING_VPW_BIT)
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#define LCD_VERTTIMING_VPW_N(N) ((((N)-1) << LCD_VERTTIMING_VPW_BIT) & LCD_VERTTIMING_VPW_MASK)
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#define LCD_VERTTIMING_LPP_BIT 0
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#define LCD_VERTTIMING_LPP_MASK (0x3FF << LCD_VERTTIMING_LPP_BIT)
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#define LCD_VERTTIMING_LPP_N(N) ((((N)-1) << LCD_VERTTIMING_LPP_BIT) & LCD_VERTTIMING_LPP_MASK)
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#define LCD_CLKCONTROL (AU1100_LCD_BASE + 0x14)
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#define LCD_CLKCONTROL_IB (1<<18)
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#define LCD_CLKCONTROL_IC (1<<17)
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#define LCD_CLKCONTROL_IH (1<<16)
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#define LCD_CLKCONTROL_IV (1<<15)
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#define LCD_CLKCONTROL_BF_BIT 10
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#define LCD_CLKCONTROL_BF_MASK (0x1F << LCD_CLKCONTROL_BF_BIT)
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#define LCD_CLKCONTROL_BF_N(N) ((((N)-1) << LCD_CLKCONTROL_BF_BIT) & LCD_CLKCONTROL_BF_MASK)
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#define LCD_CLKCONTROL_PCD_BIT 0
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#define LCD_CLKCONTROL_PCD_MASK (0x3FF << LCD_CLKCONTROL_PCD_BIT)
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#define LCD_CLKCONTROL_PCD_N(N) (((N) << LCD_CLKCONTROL_PCD_BIT) & LCD_CLKCONTROL_PCD_MASK)
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#define LCD_DMAADDR0 (AU1100_LCD_BASE + 0x18)
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#define LCD_DMAADDR1 (AU1100_LCD_BASE + 0x1C)
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#define LCD_DMA_SA_BIT 5
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#define LCD_DMA_SA_MASK (0x7FFFFFF << LCD_DMA_SA_BIT)
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#define LCD_DMA_SA_N(N) ((N) & LCD_DMA_SA_MASK)
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#define LCD_WORDS (AU1100_LCD_BASE + 0x20)
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#define LCD_WRD_WRDS_BIT 0
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#define LCD_WRD_WRDS_MASK (0xFFFFFFFF << LCD_WRD_WRDS_BIT)
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#define LCD_WRD_WRDS_N(N) ((((N)-1) << LCD_WRD_WRDS_BIT) & LCD_WRD_WRDS_MASK)
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#define LCD_PWMDIV (AU1100_LCD_BASE + 0x24)
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#define LCD_PWMDIV_EN (1<<12)
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#define LCD_PWMDIV_PWMDIV_BIT 0
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#define LCD_PWMDIV_PWMDIV_MASK (0xFFF << LCD_PWMDIV_PWMDIV_BIT)
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#define LCD_PWMDIV_PWMDIV_N(N) ((((N)-1) << LCD_PWMDIV_PWMDIV_BIT) & LCD_PWMDIV_PWMDIV_MASK)
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#define LCD_PWMHI (AU1100_LCD_BASE + 0x28)
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#define LCD_PWMHI_PWMHI1_BIT 12
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#define LCD_PWMHI_PWMHI1_MASK (0xFFF << LCD_PWMHI_PWMHI1_BIT)
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#define LCD_PWMHI_PWMHI1_N(N) (((N) << LCD_PWMHI_PWMHI1_BIT) & LCD_PWMHI_PWMHI1_MASK)
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#define LCD_PWMHI_PWMHI0_BIT 0
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#define LCD_PWMHI_PWMHI0_MASK (0xFFF << LCD_PWMHI_PWMHI0_BIT)
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#define LCD_PWMHI_PWMHI0_N(N) (((N) << LCD_PWMHI_PWMHI0_BIT) & LCD_PWMHI_PWMHI0_MASK)
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#define LCD_PALLETTEBASE (AU1100_LCD_BASE + 0x400)
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#define LCD_PALLETTE_MONO_MI_BIT 0
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#define LCD_PALLETTE_MONO_MI_MASK (0xF << LCD_PALLETTE_MONO_MI_BIT)
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#define LCD_PALLETTE_MONO_MI_N(N) (((N)<< LCD_PALLETTE_MONO_MI_BIT) & LCD_PALLETTE_MONO_MI_MASK)
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#define LCD_PALLETTE_COLOR_RI_BIT 8
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#define LCD_PALLETTE_COLOR_RI_MASK (0xF << LCD_PALLETTE_COLOR_RI_BIT)
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#define LCD_PALLETTE_COLOR_RI_N(N) (((N)<< LCD_PALLETTE_COLOR_RI_BIT) & LCD_PALLETTE_COLOR_RI_MASK)
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#define LCD_PALLETTE_COLOR_GI_BIT 4
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#define LCD_PALLETTE_COLOR_GI_MASK (0xF << LCD_PALLETTE_COLOR_GI_BIT)
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#define LCD_PALLETTE_COLOR_GI_N(N) (((N)<< LCD_PALLETTE_COLOR_GI_BIT) & LCD_PALLETTE_COLOR_GI_MASK)
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#define LCD_PALLETTE_COLOR_BI_BIT 0
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#define LCD_PALLETTE_COLOR_BI_MASK (0xF << LCD_PALLETTE_COLOR_BI_BIT)
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#define LCD_PALLETTE_COLOR_BI_N(N) (((N)<< LCD_PALLETTE_COLOR_BI_BIT) & LCD_PALLETTE_COLOR_BI_MASK)
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#define LCD_PALLETTE_TFT_DC_BIT 0
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#define LCD_PALLETTE_TFT_DC_MASK (0xFFFF << LCD_PALLETTE_TFT_DC_BIT)
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#define LCD_PALLETTE_TFT_DC_N(N) (((N)<< LCD_PALLETTE_TFT_DC_BIT) & LCD_PALLETTE_TFT_DC_MASK)
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/********************************************************************/
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/* List of panels known to work with the AU1100 LCD controller.
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* To add a new panel, enter the same specifications as the
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* Generic_TFT one, and MAKE SURE that it doesn't conflicts
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* with the controller restrictions. Restrictions are:
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*
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* STN color panels: max_bpp <= 12
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* STN mono panels: max_bpp <= 4
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* TFT panels: max_bpp <= 16
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* max_xres <= 800
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* max_yres <= 600
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*/
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static struct au1100fb_panel known_lcd_panels[] =
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{
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/* 800x600x16bpp CRT */
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[0] = {
297+
.name = "CRT_800x600_16",
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.xres = 800,
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.yres = 600,
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.bpp = 16,
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.control_base = 0x0004886A |
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LCD_CONTROL_DEFAULT_PO | LCD_CONTROL_DEFAULT_SBPPF |
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LCD_CONTROL_BPP_16 | LCD_CONTROL_SBB_4,
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.clkcontrol_base = 0x00020000,
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.horztiming = 0x005aff1f,
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.verttiming = 0x16000e57,
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},
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/* just the standard LCD */
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[1] = {
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.name = "WWPC LCD",
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.xres = 240,
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.yres = 320,
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.bpp = 16,
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.control_base = 0x0006806A,
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.horztiming = 0x0A1010EF,
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.verttiming = 0x0301013F,
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.clkcontrol_base = 0x00018001,
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},
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/* Sharp 320x240 TFT panel */
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[2] = {
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.name = "Sharp_LQ038Q5DR01",
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.xres = 320,
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.yres = 240,
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.bpp = 16,
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.control_base =
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( LCD_CONTROL_SBPPF_565
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| LCD_CONTROL_C
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| LCD_CONTROL_SM_0
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| LCD_CONTROL_DEFAULT_PO
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| LCD_CONTROL_PT
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| LCD_CONTROL_PC
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| LCD_CONTROL_BPP_16 ),
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.horztiming =
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( LCD_HORZTIMING_HN2_N(8)
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| LCD_HORZTIMING_HN1_N(60)
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| LCD_HORZTIMING_HPW_N(12)
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| LCD_HORZTIMING_PPL_N(320) ),
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.verttiming =
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( LCD_VERTTIMING_VN2_N(5)
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| LCD_VERTTIMING_VN1_N(17)
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| LCD_VERTTIMING_VPW_N(1)
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| LCD_VERTTIMING_LPP_N(240) ),
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.clkcontrol_base = LCD_CLKCONTROL_PCD_N(1),
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},
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/* Hitachi SP14Q005 and possibly others */
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[3] = {
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.name = "Hitachi_SP14Qxxx",
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.xres = 320,
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.yres = 240,
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.bpp = 4,
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.control_base =
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( LCD_CONTROL_C
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| LCD_CONTROL_BPP_4 ),
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.horztiming =
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( LCD_HORZTIMING_HN2_N(1)
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| LCD_HORZTIMING_HN1_N(1)
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| LCD_HORZTIMING_HPW_N(1)
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| LCD_HORZTIMING_PPL_N(320) ),
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.verttiming =
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( LCD_VERTTIMING_VN2_N(1)
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| LCD_VERTTIMING_VN1_N(1)
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| LCD_VERTTIMING_VPW_N(1)
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| LCD_VERTTIMING_LPP_N(240) ),
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.clkcontrol_base = LCD_CLKCONTROL_PCD_N(4),
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},
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/* Generic 640x480 TFT panel */
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[4] = {
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.name = "TFT_640x480_16",
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.xres = 640,
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.yres = 480,
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.bpp = 16,
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.control_base = 0x004806a | LCD_CONTROL_DEFAULT_PO,
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.horztiming = 0x3434d67f,
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.verttiming = 0x0e0e39df,
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.clkcontrol_base = LCD_CLKCONTROL_PCD_N(1),
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},
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/* Pb1100 LCDB 640x480 PrimeView TFT panel */
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[5] = {
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.name = "PrimeView_640x480_16",
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.xres = 640,
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.yres = 480,
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.bpp = 16,
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.control_base = 0x0004886a | LCD_CONTROL_DEFAULT_PO,
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.horztiming = 0x0e4bfe7f,
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.verttiming = 0x210805df,
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.clkcontrol_base = 0x00038001,
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},
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};
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/********************************************************************/
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/* Inline helpers */
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#define panel_is_dual(panel) (panel->control_base & LCD_CONTROL_DP)
398+
#define panel_is_active(panel)(panel->control_base & LCD_CONTROL_PT)
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#define panel_is_color(panel) (panel->control_base & LCD_CONTROL_PC)
400+
#define panel_swap_rgb(panel) (panel->control_base & LCD_CONTROL_CCO)
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65402
#if defined(CONFIG_COMPILE_TEST) && !defined(CONFIG_MIPS)
66403
/* This is only defined to be able to compile this driver on non-mips platforms */

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