|
120 | 120 | }; |
121 | 121 |
|
122 | 122 | &k2g_pinctrl { |
123 | | - uart0_pins: pinmux_uart0_pins { |
| 123 | + uart0_pins: uart0-pins { |
124 | 124 | pinctrl-single,pins = < |
125 | 125 | K2G_CORE_IOPAD(0x11cc) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* uart0_rxd.uart0_rxd */ |
126 | 126 | K2G_CORE_IOPAD(0x11d0) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */ |
127 | 127 | >; |
128 | 128 | }; |
129 | 129 |
|
130 | | - mmc0_pins: pinmux_mmc0_pins { |
| 130 | + mmc0_pins: mmc0-pins { |
131 | 131 | pinctrl-single,pins = < |
132 | 132 | K2G_CORE_IOPAD(0x1300) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE2) /* mmc0_dat3.mmc0_dat3 */ |
133 | 133 | K2G_CORE_IOPAD(0x1304) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE2) /* mmc0_dat2.mmc0_dat2 */ |
|
139 | 139 | >; |
140 | 140 | }; |
141 | 141 |
|
142 | | - mmc1_pins: pinmux_mmc1_pins { |
| 142 | + mmc1_pins: mmc1-pins { |
143 | 143 | pinctrl-single,pins = < |
144 | 144 | K2G_CORE_IOPAD(0x10ec) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat7.mmc1_dat7 */ |
145 | 145 | K2G_CORE_IOPAD(0x10f0) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat6.mmc1_dat6 */ |
|
154 | 154 | >; |
155 | 155 | }; |
156 | 156 |
|
157 | | - i2c0_pins: pinmux_i2c0_pins { |
| 157 | + i2c0_pins: i2c0-pins { |
158 | 158 | pinctrl-single,pins = < |
159 | 159 | K2G_CORE_IOPAD(0x137c) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */ |
160 | 160 | K2G_CORE_IOPAD(0x1380) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */ |
161 | 161 | >; |
162 | 162 | }; |
163 | 163 |
|
164 | | - i2c1_pins: pinmux_i2c1_pins { |
| 164 | + i2c1_pins: i2c1-pins { |
165 | 165 | pinctrl-single,pins = < |
166 | 166 | K2G_CORE_IOPAD(0x1384) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* i2c1_scl.i2c1_scl */ |
167 | 167 | K2G_CORE_IOPAD(0x1388) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* i2c1_sda.i2c1_sda */ |
168 | 168 | >; |
169 | 169 | }; |
170 | 170 |
|
171 | | - ecap0_pins: ecap0_pins { |
| 171 | + ecap0_pins: ecap0-pins { |
172 | 172 | pinctrl-single,pins = < |
173 | 173 | K2G_CORE_IOPAD(0x1374) (BUFFER_CLASS_B | MUX_MODE4) /* pr1_mdio_data.ecap0_in_apwm0_out */ |
174 | 174 | >; |
175 | 175 | }; |
176 | 176 |
|
177 | | - spi1_pins: pinmux_spi1_pins { |
| 177 | + spi1_pins: spi1-pins { |
178 | 178 | pinctrl-single,pins = < |
179 | 179 | K2G_CORE_IOPAD(0x11a4) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* spi1_scs0.spi1_scs0 */ |
180 | 180 | K2G_CORE_IOPAD(0x11ac) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* spi1_clk.spi1_clk */ |
|
183 | 183 | >; |
184 | 184 | }; |
185 | 185 |
|
186 | | - qspi_pins: pinmux_qspi_pins { |
| 186 | + qspi_pins: qspi-pins { |
187 | 187 | pinctrl-single,pins = < |
188 | 188 | K2G_CORE_IOPAD(0x1204) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_clk.qspi_clk */ |
189 | 189 | K2G_CORE_IOPAD(0x1208) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_rclk.qspi_rclk */ |
|
195 | 195 | >; |
196 | 196 | }; |
197 | 197 |
|
198 | | - uart2_pins: pinmux_uart2_pins { |
| 198 | + uart2_pins: uart2-pins { |
199 | 199 | pinctrl-single,pins = < |
200 | 200 | K2G_CORE_IOPAD(0x11ec) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* uart2_rxd.uart2_rxd */ |
201 | 201 | K2G_CORE_IOPAD(0x11f0) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE0) /* uart2_txd.uart2_txd */ |
202 | 202 | >; |
203 | 203 | }; |
204 | 204 |
|
205 | | - dcan0_pins: pinmux_dcan0_pins { |
| 205 | + dcan0_pins: dcan0-pins { |
206 | 206 | pinctrl-single,pins = < |
207 | 207 | K2G_CORE_IOPAD(0x11fc) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dcan0tx.dcan0tx */ |
208 | 208 | K2G_CORE_IOPAD(0x1200) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE0) /* dcan0rx.dcan0rx */ |
209 | 209 | >; |
210 | 210 | }; |
211 | 211 |
|
212 | | - dcan1_pins: pinmux_dcan1_pins { |
| 212 | + dcan1_pins: dcan1-pins { |
213 | 213 | pinctrl-single,pins = < |
214 | 214 | K2G_CORE_IOPAD(0x1224) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE1) /* qspicsn2.dcan1tx */ |
215 | 215 | K2G_CORE_IOPAD(0x1228) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE1) /* qspicsn3.dcan1rx */ |
216 | 216 | >; |
217 | 217 | }; |
218 | 218 |
|
219 | | - emac_pins: pinmux_emac_pins { |
| 219 | + emac_pins: emac-pins { |
220 | 220 | pinctrl-single,pins = < |
221 | | - K2G_CORE_IOPAD(0x113C) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXD1.RGMII_RXD1 */ |
| 221 | + K2G_CORE_IOPAD(0x113c) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXD1.RGMII_RXD1 */ |
222 | 222 | K2G_CORE_IOPAD(0x1138) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXD2.RGMII_RXD2 */ |
223 | 223 | K2G_CORE_IOPAD(0x1134) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXD3.RGMII_RXD3 */ |
224 | 224 | K2G_CORE_IOPAD(0x1140) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXD0.RGMII_RXD0 */ |
225 | 225 | K2G_CORE_IOPAD(0x1178) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXD0.RGMII_TXD0 */ |
226 | 226 | K2G_CORE_IOPAD(0x1174) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXD1.RGMII_TXD1 */ |
227 | 227 | K2G_CORE_IOPAD(0x1170) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXD2.RGMII_TXD2 */ |
228 | | - K2G_CORE_IOPAD(0x116C) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXD3.RGMII_TXD3 */ |
| 228 | + K2G_CORE_IOPAD(0x116c) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXD3.RGMII_TXD3 */ |
229 | 229 | K2G_CORE_IOPAD(0x1154) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXCLK.RGMII_TXC */ |
230 | | - K2G_CORE_IOPAD(0x117C) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXEN.RGMII_TXCTL */ |
| 230 | + K2G_CORE_IOPAD(0x117c) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXEN.RGMII_TXCTL */ |
231 | 231 | K2G_CORE_IOPAD(0x1120) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXCLK.RGMII_RXC */ |
232 | 232 | K2G_CORE_IOPAD(0x1144) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXDV.RGMII_RXCTL */ |
233 | 233 | >; |
234 | 234 | }; |
235 | 235 |
|
236 | | - mdio_pins: pinmux_mdio_pins { |
| 236 | + mdio_pins: mdio-pins { |
237 | 237 | pinctrl-single,pins = < |
238 | | - K2G_CORE_IOPAD(0x118C) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* MDIO_CLK.MDIO_CLK */ |
| 238 | + K2G_CORE_IOPAD(0x118c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* MDIO_CLK.MDIO_CLK */ |
239 | 239 | K2G_CORE_IOPAD(0x1188) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* MDIO_DATA.MDIO_DATA */ |
240 | 240 | >; |
241 | 241 | }; |
242 | 242 |
|
243 | | - vout_pins: pinmux_vout_pins { |
| 243 | + vout_pins: vout-pins { |
244 | 244 | pinctrl-single,pins = < |
245 | 245 | K2G_CORE_IOPAD(0x1078) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata23.dssdata23 */ |
246 | 246 | K2G_CORE_IOPAD(0x107c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata22.dssdata22 */ |
|
274 | 274 | >; |
275 | 275 | }; |
276 | 276 |
|
277 | | - mcasp2_pins: pinmux_mcasp2_pins { |
| 277 | + mcasp2_pins: mcasp2-pins { |
278 | 278 | pinctrl-single,pins = < |
279 | 279 | K2G_CORE_IOPAD(0x1234) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE4) /* pr0_pru_gpo2.mcasp2_axr2 */ |
280 | 280 | K2G_CORE_IOPAD(0x1238) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE4) /* pr0_pru_gpo3.mcasp2_axr3 */ |
|
424 | 424 | }; |
425 | 425 | partition@4 { |
426 | 426 | label = "QSPI.kernel"; |
427 | | - reg = <0x001C0000 0x0800000>; |
| 427 | + reg = <0x001c0000 0x0800000>; |
428 | 428 | }; |
429 | 429 | partition@5 { |
430 | 430 | label = "QSPI.file-system"; |
431 | | - reg = <0x009C0000 0x3640000>; |
| 431 | + reg = <0x009c0000 0x3640000>; |
432 | 432 | }; |
433 | 433 | }; |
434 | 434 | }; |
|
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