drm/i915/mtl: Support HBR3 rate with C10 phy and eDP in MTL

ckborah · jnikula · commit ce4941c2d645 · 2023-10-30T13:48:41.000+02:00
eDP specification supports HBR3 link rate since v1.4a. Moreover, C10 phy can support HBR3 link rate for both DP and eDP. Therefore, do not clamp the supported rates for eDP at 6.75Gbps. Cc: <stable@vger.kernel.org> BSpec: 70073 74224 Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com> Reviewed-by: Mika Kahola <mika.kahola@intel.com> Signed-off-by: Mika Kahola <mika.kahola@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231018113622.2761997-1-chaitanya.kumar.borah@intel.com (cherry picked from commit a343165) Signed-off-by: Jani Nikula <jani.nikula@intel.com>
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -430,7 +430,7 @@ static int mtl_max_source_rate(struct intel_dp *intel_dp)
 	enum phy phy = intel_port_to_phy(i915, dig_port->base.port);
 
 	if (intel_is_c10phy(i915, phy))
-		return intel_dp_is_edp(intel_dp) ? 675000 : 810000;
+		return 810000;
 
 	return 2000000;
 }

Original file line number	Diff line number	Diff line change
`@@ -430,7 +430,7 @@ static int mtl_max_source_rate(struct intel_dp *intel_dp)`
`430`	`430`	`enum phy phy = intel_port_to_phy(i915, dig_port->base.port);`
`431`	`431`
`432`	`432`	`if (intel_is_c10phy(i915, phy))`
`433`		`- return intel_dp_is_edp(intel_dp) ? 675000 : 810000;`
	`433`	`+ return 810000;`
`434`	`434`
`435`	`435`	`return 2000000;`
`436`	`436`	`}`