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| 1 | +# SPDX-License-Identifier: GPL-2.0 |
| 2 | +%YAML 1.2 |
| 3 | +--- |
| 4 | +$id: http://devicetree.org/schemas/mmc/mtk-sd.yaml# |
| 5 | +$schema: http://devicetree.org/meta-schemas/core.yaml# |
| 6 | + |
| 7 | +title: MTK MSDC Storage Host Controller Binding |
| 8 | + |
| 9 | +maintainers: |
| 10 | + - Chaotian Jing <chaotian.jing@mediatek.com> |
| 11 | + - Wenbin Mei <wenbin.mei@mediatek.com> |
| 12 | + |
| 13 | +allOf: |
| 14 | + - $ref: mmc-controller.yaml# |
| 15 | + |
| 16 | +properties: |
| 17 | + compatible: |
| 18 | + oneOf: |
| 19 | + - enum: |
| 20 | + - mediatek,mt2701-mmc |
| 21 | + - mediatek,mt2712-mmc |
| 22 | + - mediatek,mt6779-mmc |
| 23 | + - mediatek,mt7620-mmc |
| 24 | + - mediatek,mt7622-mmc |
| 25 | + - mediatek,mt8135-mmc |
| 26 | + - mediatek,mt8173-mmc |
| 27 | + - mediatek,mt8183-mmc |
| 28 | + - mediatek,mt8516-mmc |
| 29 | + - items: |
| 30 | + - const: mediatek,mt7623-mmc |
| 31 | + - const: mediatek,mt2701-mmc |
| 32 | + - items: |
| 33 | + - const: mediatek,mt8192-mmc |
| 34 | + - const: mediatek,mt8183-mmc |
| 35 | + |
| 36 | + clocks: |
| 37 | + description: |
| 38 | + Should contain phandle for the clock feeding the MMC controller. |
| 39 | + minItems: 2 |
| 40 | + maxItems: 8 |
| 41 | + items: |
| 42 | + - description: source clock (required). |
| 43 | + - description: HCLK which used for host (required). |
| 44 | + - description: independent source clock gate (required for MT2712). |
| 45 | + - description: bus clock used for internal register access (required for MT2712 MSDC0/3). |
| 46 | + - description: msdc subsys clock gate (required for MT8192). |
| 47 | + - description: peripheral bus clock gate (required for MT8192). |
| 48 | + - description: AXI bus clock gate (required for MT8192). |
| 49 | + - description: AHB bus clock gate (required for MT8192). |
| 50 | + |
| 51 | + clock-names: |
| 52 | + minItems: 2 |
| 53 | + maxItems: 8 |
| 54 | + items: |
| 55 | + - const: source |
| 56 | + - const: hclk |
| 57 | + - const: source_cg |
| 58 | + - const: bus_clk |
| 59 | + - const: sys_cg |
| 60 | + - const: pclk_cg |
| 61 | + - const: axi_cg |
| 62 | + - const: ahb_cg |
| 63 | + |
| 64 | + pinctrl-names: |
| 65 | + items: |
| 66 | + - const: default |
| 67 | + - const: state_uhs |
| 68 | + |
| 69 | + pinctrl-0: |
| 70 | + description: |
| 71 | + should contain default/high speed pin ctrl. |
| 72 | + maxItems: 1 |
| 73 | + |
| 74 | + pinctrl-1: |
| 75 | + description: |
| 76 | + should contain uhs mode pin ctrl. |
| 77 | + maxItems: 1 |
| 78 | + |
| 79 | + assigned-clocks: |
| 80 | + description: |
| 81 | + PLL of the source clock. |
| 82 | + maxItems: 1 |
| 83 | + |
| 84 | + assigned-clock-parents: |
| 85 | + description: |
| 86 | + parent of source clock, used for HS400 mode to get 400Mhz source clock. |
| 87 | + maxItems: 1 |
| 88 | + |
| 89 | + hs400-ds-delay: |
| 90 | + $ref: /schemas/types.yaml#/definitions/uint32 |
| 91 | + description: |
| 92 | + HS400 DS delay setting. |
| 93 | + minimum: 0 |
| 94 | + maximum: 0xffffffff |
| 95 | + |
| 96 | + mediatek,hs200-cmd-int-delay: |
| 97 | + $ref: /schemas/types.yaml#/definitions/uint32 |
| 98 | + description: |
| 99 | + HS200 command internal delay setting. |
| 100 | + This field has total 32 stages. |
| 101 | + The value is an integer from 0 to 31. |
| 102 | + minimum: 0 |
| 103 | + maximum: 31 |
| 104 | + |
| 105 | + mediatek,hs400-cmd-int-delay: |
| 106 | + $ref: /schemas/types.yaml#/definitions/uint32 |
| 107 | + description: |
| 108 | + HS400 command internal delay setting. |
| 109 | + This field has total 32 stages. |
| 110 | + The value is an integer from 0 to 31. |
| 111 | + minimum: 0 |
| 112 | + maximum: 31 |
| 113 | + |
| 114 | + mediatek,hs400-cmd-resp-sel-rising: |
| 115 | + $ref: /schemas/types.yaml#/definitions/flag |
| 116 | + description: |
| 117 | + HS400 command response sample selection. |
| 118 | + If present, HS400 command responses are sampled on rising edges. |
| 119 | + If not present, HS400 command responses are sampled on falling edges. |
| 120 | + |
| 121 | + mediatek,latch-ck: |
| 122 | + $ref: /schemas/types.yaml#/definitions/uint32 |
| 123 | + description: |
| 124 | + Some SoCs do not support enhance_rx, need set correct latch-ck to avoid |
| 125 | + data crc error caused by stop clock(fifo full) Valid range = [0:0x7]. |
| 126 | + if not present, default value is 0. |
| 127 | + applied to compatible "mediatek,mt2701-mmc". |
| 128 | + minimum: 0 |
| 129 | + maximum: 7 |
| 130 | + |
| 131 | + resets: |
| 132 | + maxItems: 1 |
| 133 | + |
| 134 | + reset-names: |
| 135 | + const: hrst |
| 136 | + |
| 137 | +required: |
| 138 | + - compatible |
| 139 | + - reg |
| 140 | + - interrupts |
| 141 | + - clocks |
| 142 | + - clock-names |
| 143 | + - pinctrl-names |
| 144 | + - pinctrl-0 |
| 145 | + - pinctrl-1 |
| 146 | + - vmmc-supply |
| 147 | + - vqmmc-supply |
| 148 | + |
| 149 | +unevaluatedProperties: false |
| 150 | + |
| 151 | +examples: |
| 152 | + - | |
| 153 | + #include <dt-bindings/interrupt-controller/irq.h> |
| 154 | + #include <dt-bindings/interrupt-controller/arm-gic.h> |
| 155 | + #include <dt-bindings/clock/mt8173-clk.h> |
| 156 | + mmc0: mmc@11230000 { |
| 157 | + compatible = "mediatek,mt8173-mmc"; |
| 158 | + reg = <0x11230000 0x1000>; |
| 159 | + interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_LOW>; |
| 160 | + vmmc-supply = <&mt6397_vemc_3v3_reg>; |
| 161 | + vqmmc-supply = <&mt6397_vio18_reg>; |
| 162 | + clocks = <&pericfg CLK_PERI_MSDC30_0>, |
| 163 | + <&topckgen CLK_TOP_MSDC50_0_H_SEL>; |
| 164 | + clock-names = "source", "hclk"; |
| 165 | + pinctrl-names = "default", "state_uhs"; |
| 166 | + pinctrl-0 = <&mmc0_pins_default>; |
| 167 | + pinctrl-1 = <&mmc0_pins_uhs>; |
| 168 | + assigned-clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>; |
| 169 | + assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>; |
| 170 | + hs400-ds-delay = <0x14015>; |
| 171 | + mediatek,hs200-cmd-int-delay = <26>; |
| 172 | + mediatek,hs400-cmd-int-delay = <14>; |
| 173 | + mediatek,hs400-cmd-resp-sel-rising; |
| 174 | + }; |
| 175 | +
|
| 176 | +... |
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