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21 | 21 | * byte ordering of Linux running on ARM64, so no special handling is required. |
22 | 22 | */ |
23 | 23 |
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24 | | -/* |
25 | | - * These Hyper-V registers provide information equivalent to the CPUID |
26 | | - * instruction on x86/x64. |
27 | | - */ |
28 | | -#define HV_REGISTER_HYPERVISOR_VERSION 0x00000100 /*CPUID 0x40000002 */ |
29 | | -#define HV_REGISTER_FEATURES 0x00000200 /*CPUID 0x40000003 */ |
30 | | -#define HV_REGISTER_ENLIGHTENMENTS 0x00000201 /*CPUID 0x40000004 */ |
31 | | - |
32 | 24 | /* |
33 | 25 | * Group C Features. See the asm-generic version of hyperv-tlfs.h |
34 | 26 | * for a description of Feature Groups. |
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41 | 33 | #define HV_STIMER_DIRECT_MODE_AVAILABLE BIT(13) |
42 | 34 |
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43 | 35 | /* |
44 | | - * Synthetic register definitions equivalent to MSRs on x86/x64 |
| 36 | + * To support arch-generic code calling hv_set/get_register: |
| 37 | + * - On x86, HV_MSR_ indicates an MSR accessed via rdmsrl/wrmsrl |
| 38 | + * - On ARM, HV_MSR_ indicates a VP register accessed via hypercall |
45 | 39 | */ |
46 | | -#define HV_REGISTER_CRASH_P0 0x00000210 |
47 | | -#define HV_REGISTER_CRASH_P1 0x00000211 |
48 | | -#define HV_REGISTER_CRASH_P2 0x00000212 |
49 | | -#define HV_REGISTER_CRASH_P3 0x00000213 |
50 | | -#define HV_REGISTER_CRASH_P4 0x00000214 |
51 | | -#define HV_REGISTER_CRASH_CTL 0x00000215 |
| 40 | +#define HV_MSR_CRASH_P0 (HV_REGISTER_GUEST_CRASH_P0) |
| 41 | +#define HV_MSR_CRASH_P1 (HV_REGISTER_GUEST_CRASH_P1) |
| 42 | +#define HV_MSR_CRASH_P2 (HV_REGISTER_GUEST_CRASH_P2) |
| 43 | +#define HV_MSR_CRASH_P3 (HV_REGISTER_GUEST_CRASH_P3) |
| 44 | +#define HV_MSR_CRASH_P4 (HV_REGISTER_GUEST_CRASH_P4) |
| 45 | +#define HV_MSR_CRASH_CTL (HV_REGISTER_GUEST_CRASH_CTL) |
52 | 46 |
|
53 | | -#define HV_REGISTER_GUEST_OSID 0x00090002 |
54 | | -#define HV_REGISTER_VP_INDEX 0x00090003 |
55 | | -#define HV_REGISTER_TIME_REF_COUNT 0x00090004 |
56 | | -#define HV_REGISTER_REFERENCE_TSC 0x00090017 |
| 47 | +#define HV_MSR_VP_INDEX (HV_REGISTER_VP_INDEX) |
| 48 | +#define HV_MSR_TIME_REF_COUNT (HV_REGISTER_TIME_REF_COUNT) |
| 49 | +#define HV_MSR_REFERENCE_TSC (HV_REGISTER_REFERENCE_TSC) |
57 | 50 |
|
58 | | -#define HV_REGISTER_SINT0 0x000A0000 |
59 | | -#define HV_REGISTER_SCONTROL 0x000A0010 |
60 | | -#define HV_REGISTER_SIEFP 0x000A0012 |
61 | | -#define HV_REGISTER_SIMP 0x000A0013 |
62 | | -#define HV_REGISTER_EOM 0x000A0014 |
| 51 | +#define HV_MSR_SINT0 (HV_REGISTER_SINT0) |
| 52 | +#define HV_MSR_SCONTROL (HV_REGISTER_SCONTROL) |
| 53 | +#define HV_MSR_SIEFP (HV_REGISTER_SIEFP) |
| 54 | +#define HV_MSR_SIMP (HV_REGISTER_SIMP) |
| 55 | +#define HV_MSR_EOM (HV_REGISTER_EOM) |
63 | 56 |
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64 | | -#define HV_REGISTER_STIMER0_CONFIG 0x000B0000 |
65 | | -#define HV_REGISTER_STIMER0_COUNT 0x000B0001 |
| 57 | +#define HV_MSR_STIMER0_CONFIG (HV_REGISTER_STIMER0_CONFIG) |
| 58 | +#define HV_MSR_STIMER0_COUNT (HV_REGISTER_STIMER0_COUNT) |
66 | 59 |
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67 | 60 | union hv_msi_entry { |
68 | 61 | u64 as_uint64[2]; |
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