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VDavid003Sylwester Nawrocki
VDavid003
authored and
Sylwester Nawrocki
committed
clk: samsung: Make exynos850_register_cmu shared
Rename exynos850_register_cmu to exynos_arm64_register_cmu and move it to a new file called "clk-exynos-arm64.c". This should have no functional changes, but it will allow this code to be shared between other arm64 Exynos SoCs, like the Exynos7885 and possibly ExynosAuto V9. Signed-off-by: David Virag <virag.david003@gmail.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Link: https://lore.kernel.org/r/20211206153124.427102-5-virag.david003@gmail.com
1 parent 77624aa commit cfe238e

4 files changed

Lines changed: 119 additions & 84 deletions

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‎drivers/clk/samsung/Makefile‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -16,6 +16,7 @@ obj-$(CONFIG_EXYNOS_5420_COMMON_CLK) += clk-exynos5-subcmu.o
1616
obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos5433.o
1717
obj-$(CONFIG_EXYNOS_AUDSS_CLK_CON) += clk-exynos-audss.o
1818
obj-$(CONFIG_EXYNOS_CLKOUT) += clk-exynos-clkout.o
19+
obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos-arm64.o
1920
obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos7.o
2021
obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos850.o
2122
obj-$(CONFIG_S3C2410_COMMON_CLK)+= clk-s3c2410.o

‎drivers/clk/samsung/clk-exynos-arm64.c‎

Lines changed: 94 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,94 @@
1+
// SPDX-License-Identifier: GPL-2.0-only
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/*
3+
* Copyright (C) 2021 Linaro Ltd.
4+
* Copyright (C) 2021 Dávid Virág <virag.david003@gmail.com>
5+
* Author: Sam Protsenko <semen.protsenko@linaro.org>
6+
* Author: Dávid Virág <virag.david003@gmail.com>
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*
8+
* This file contains shared functions used by some arm64 Exynos SoCs,
9+
* such as Exynos7885 or Exynos850 to register and init CMUs.
10+
*/
11+
#include <linux/clk.h>
12+
#include <linux/of_address.h>
13+
14+
#include "clk-exynos-arm64.h"
15+
16+
/* Gate register bits */
17+
#define GATE_MANUAL BIT(20)
18+
#define GATE_ENABLE_HWACG BIT(28)
19+
20+
/* Gate register offsets range */
21+
#define GATE_OFF_START 0x2000
22+
#define GATE_OFF_END 0x2fff
23+
24+
/**
25+
* exynos_arm64_init_clocks - Set clocks initial configuration
26+
* @np: CMU device tree node with "reg" property (CMU addr)
27+
* @reg_offs: Register offsets array for clocks to init
28+
* @reg_offs_len: Number of register offsets in reg_offs array
29+
*
30+
* Set manual control mode for all gate clocks.
31+
*/
32+
static void __init exynos_arm64_init_clocks(struct device_node *np,
33+
const unsigned long *reg_offs, size_t reg_offs_len)
34+
{
35+
void __iomem *reg_base;
36+
size_t i;
37+
38+
reg_base = of_iomap(np, 0);
39+
if (!reg_base)
40+
panic("%s: failed to map registers\n", __func__);
41+
42+
for (i = 0; i < reg_offs_len; ++i) {
43+
void __iomem *reg = reg_base + reg_offs[i];
44+
u32 val;
45+
46+
/* Modify only gate clock registers */
47+
if (reg_offs[i] < GATE_OFF_START || reg_offs[i] > GATE_OFF_END)
48+
continue;
49+
50+
val = readl(reg);
51+
val |= GATE_MANUAL;
52+
val &= ~GATE_ENABLE_HWACG;
53+
writel(val, reg);
54+
}
55+
56+
iounmap(reg_base);
57+
}
58+
59+
/**
60+
* exynos_arm64_register_cmu - Register specified Exynos CMU domain
61+
* @dev: Device object; may be NULL if this function is not being
62+
* called from platform driver probe function
63+
* @np: CMU device tree node
64+
* @cmu: CMU data
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*
66+
* Register specified CMU domain, which includes next steps:
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*
68+
* 1. Enable parent clock of @cmu CMU
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* 2. Set initial registers configuration for @cmu CMU clocks
70+
* 3. Register @cmu CMU clocks using Samsung clock framework API
71+
*/
72+
void __init exynos_arm64_register_cmu(struct device *dev,
73+
struct device_node *np, const struct samsung_cmu_info *cmu)
74+
{
75+
/* Keep CMU parent clock running (needed for CMU registers access) */
76+
if (cmu->clk_name) {
77+
struct clk *parent_clk;
78+
79+
if (dev)
80+
parent_clk = clk_get(dev, cmu->clk_name);
81+
else
82+
parent_clk = of_clk_get_by_name(np, cmu->clk_name);
83+
84+
if (IS_ERR(parent_clk)) {
85+
pr_err("%s: could not find bus clock %s; err = %ld\n",
86+
__func__, cmu->clk_name, PTR_ERR(parent_clk));
87+
} else {
88+
clk_prepare_enable(parent_clk);
89+
}
90+
}
91+
92+
exynos_arm64_init_clocks(np, cmu->clk_regs, cmu->nr_clk_regs);
93+
samsung_cmu_register_one(np, cmu);
94+
}

‎drivers/clk/samsung/clk-exynos-arm64.h‎

Lines changed: 20 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,20 @@
1+
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
3+
* Copyright (C) 2021 Linaro Ltd.
4+
* Copyright (C) 2021 Dávid Virág <virag.david003@gmail.com>
5+
* Author: Sam Protsenko <semen.protsenko@linaro.org>
6+
* Author: Dávid Virág <virag.david003@gmail.com>
7+
*
8+
* This file contains shared functions used by some arm64 Exynos SoCs,
9+
* such as Exynos7885 or Exynos850 to register and init CMUs.
10+
*/
11+
12+
#ifndef __CLK_EXYNOS_ARM64_H
13+
#define __CLK_EXYNOS_ARM64_H
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15+
#include "clk.h"
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17+
void exynos_arm64_register_cmu(struct device *dev,
18+
struct device_node *np, const struct samsung_cmu_info *cmu);
19+
20+
#endif /* __CLK_EXYNOS_ARM64_H */

‎drivers/clk/samsung/clk-exynos850.c‎

Lines changed: 4 additions & 84 deletions
Original file line numberDiff line numberDiff line change
@@ -9,93 +9,13 @@
99
#include <linux/clk.h>
1010
#include <linux/clk-provider.h>
1111
#include <linux/of.h>
12-
#include <linux/of_address.h>
1312
#include <linux/of_device.h>
1413
#include <linux/platform_device.h>
1514

1615
#include <dt-bindings/clock/exynos850.h>
1716

1817
#include "clk.h"
19-
20-
/* Gate register bits */
21-
#define GATE_MANUAL BIT(20)
22-
#define GATE_ENABLE_HWACG BIT(28)
23-
24-
/* Gate register offsets range */
25-
#define GATE_OFF_START 0x2000
26-
#define GATE_OFF_END 0x2fff
27-
28-
/**
29-
* exynos850_init_clocks - Set clocks initial configuration
30-
* @np: CMU device tree node with "reg" property (CMU addr)
31-
* @reg_offs: Register offsets array for clocks to init
32-
* @reg_offs_len: Number of register offsets in reg_offs array
33-
*
34-
* Set manual control mode for all gate clocks.
35-
*/
36-
static void __init exynos850_init_clocks(struct device_node *np,
37-
const unsigned long *reg_offs, size_t reg_offs_len)
38-
{
39-
void __iomem *reg_base;
40-
size_t i;
41-
42-
reg_base = of_iomap(np, 0);
43-
if (!reg_base)
44-
panic("%s: failed to map registers\n", __func__);
45-
46-
for (i = 0; i < reg_offs_len; ++i) {
47-
void __iomem *reg = reg_base + reg_offs[i];
48-
u32 val;
49-
50-
/* Modify only gate clock registers */
51-
if (reg_offs[i] < GATE_OFF_START || reg_offs[i] > GATE_OFF_END)
52-
continue;
53-
54-
val = readl(reg);
55-
val |= GATE_MANUAL;
56-
val &= ~GATE_ENABLE_HWACG;
57-
writel(val, reg);
58-
}
59-
60-
iounmap(reg_base);
61-
}
62-
63-
/**
64-
* exynos850_register_cmu - Register specified Exynos850 CMU domain
65-
* @dev: Device object; may be NULL if this function is not being
66-
* called from platform driver probe function
67-
* @np: CMU device tree node
68-
* @cmu: CMU data
69-
*
70-
* Register specified CMU domain, which includes next steps:
71-
*
72-
* 1. Enable parent clock of @cmu CMU
73-
* 2. Set initial registers configuration for @cmu CMU clocks
74-
* 3. Register @cmu CMU clocks using Samsung clock framework API
75-
*/
76-
static void __init exynos850_register_cmu(struct device *dev,
77-
struct device_node *np, const struct samsung_cmu_info *cmu)
78-
{
79-
/* Keep CMU parent clock running (needed for CMU registers access) */
80-
if (cmu->clk_name) {
81-
struct clk *parent_clk;
82-
83-
if (dev)
84-
parent_clk = clk_get(dev, cmu->clk_name);
85-
else
86-
parent_clk = of_clk_get_by_name(np, cmu->clk_name);
87-
88-
if (IS_ERR(parent_clk)) {
89-
pr_err("%s: could not find bus clock %s; err = %ld\n",
90-
__func__, cmu->clk_name, PTR_ERR(parent_clk));
91-
} else {
92-
clk_prepare_enable(parent_clk);
93-
}
94-
}
95-
96-
exynos850_init_clocks(np, cmu->clk_regs, cmu->nr_clk_regs);
97-
samsung_cmu_register_one(np, cmu);
98-
}
18+
#include "clk-exynos-arm64.h"
9919

10020
/* ---- CMU_TOP ------------------------------------------------------------- */
10121

@@ -404,7 +324,7 @@ static const struct samsung_cmu_info top_cmu_info __initconst = {
404324

405325
static void __init exynos850_cmu_top_init(struct device_node *np)
406326
{
407-
exynos850_register_cmu(NULL, np, &top_cmu_info);
327+
exynos_arm64_register_cmu(NULL, np, &top_cmu_info);
408328
}
409329

410330
/* Register CMU_TOP early, as it's a dependency for other early domains */
@@ -911,7 +831,7 @@ static const struct samsung_cmu_info peri_cmu_info __initconst = {
911831

912832
static void __init exynos850_cmu_peri_init(struct device_node *np)
913833
{
914-
exynos850_register_cmu(NULL, np, &peri_cmu_info);
834+
exynos_arm64_register_cmu(NULL, np, &peri_cmu_info);
915835
}
916836

917837
/* Register CMU_PERI early, as it's needed for MCT timer */
@@ -1098,7 +1018,7 @@ static int __init exynos850_cmu_probe(struct platform_device *pdev)
10981018
struct device *dev = &pdev->dev;
10991019

11001020
info = of_device_get_match_data(dev);
1101-
exynos850_register_cmu(dev, dev->of_node, info);
1021+
exynos_arm64_register_cmu(dev, dev->of_node, info);
11021022

11031023
return 0;
11041024
}

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