@@ -520,6 +520,28 @@ static void rg28xx_gip_sequence(struct st7701 *st7701)
520520 st7701_switch_cmd_bkx (st7701 , false, 0 );
521521}
522522
523+ static void wf40eswaa6mnn0_gip_sequence (struct st7701 * st7701 )
524+ {
525+ ST7701_WRITE (st7701 , 0xE0 , 0x00 , 0x28 , 0x02 );
526+ ST7701_WRITE (st7701 , 0xE1 , 0x08 , 0xA0 , 0x00 , 0x00 , 0x07 , 0xA0 , 0x00 ,
527+ 0x00 , 0x00 , 0x44 , 0x44 );
528+ ST7701_WRITE (st7701 , 0xE2 , 0x11 , 0x11 , 0x44 , 0x44 , 0xED , 0xA0 , 0x00 ,
529+ 0x00 , 0xEC , 0xA0 , 0x00 , 0x00 );
530+ ST7701_WRITE (st7701 , 0xE3 , 0x00 , 0x00 , 0x11 , 0x11 );
531+ ST7701_WRITE (st7701 , 0xE4 , 0x44 , 0x44 );
532+ ST7701_WRITE (st7701 , 0xE5 , 0x0A , 0xE9 , 0xD8 , 0xA0 , 0x0C , 0xEB , 0xD8 ,
533+ 0xA0 , 0x0E , 0xED , 0xD8 , 0xA0 , 0x10 , 0xEF , 0xD8 , 0xA0 );
534+ ST7701_WRITE (st7701 , 0xE6 , 0x00 , 0x00 , 0x11 , 0x11 );
535+ ST7701_WRITE (st7701 , 0xE7 , 0x44 , 0x44 );
536+ ST7701_WRITE (st7701 , 0xE8 , 0x09 , 0xE8 , 0xD8 , 0xA0 , 0x0B , 0xEA , 0xD8 ,
537+ 0xA0 , 0x0D , 0xEC , 0xD8 , 0xA0 , 0x0F , 0xEE , 0xD8 , 0xA0 );
538+ ST7701_WRITE (st7701 , 0xEB , 0x00 , 0x00 , 0xE4 , 0xE4 , 0x88 , 0x00 , 0x40 );
539+ ST7701_WRITE (st7701 , 0xEC , 0x3C , 0x00 );
540+ ST7701_WRITE (st7701 , 0xED , 0xAB , 0x89 , 0x76 , 0x54 , 0x02 , 0xFF , 0xFF ,
541+ 0xFF , 0xFF , 0xFF , 0xFF , 0x20 , 0x45 , 0x67 , 0x98 , 0xBA );
542+ ST7701_WRITE (st7701 , MIPI_DCS_SET_ADDRESS_MODE , 0 );
543+ }
544+
523545static int st7701_prepare (struct drm_panel * panel )
524546{
525547 struct st7701 * st7701 = panel_to_st7701 (panel );
@@ -1135,6 +1157,107 @@ static const struct st7701_panel_desc rg28xx_desc = {
11351157 .gip_sequence = rg28xx_gip_sequence ,
11361158};
11371159
1160+ static const struct drm_display_mode wf40eswaa6mnn0_mode = {
1161+ .clock = 18306 ,
1162+
1163+ .hdisplay = 480 ,
1164+ .hsync_start = 480 + 2 ,
1165+ .hsync_end = 480 + 2 + 45 ,
1166+ .htotal = 480 + 2 + 45 + 13 ,
1167+
1168+ .vdisplay = 480 ,
1169+ .vsync_start = 480 + 2 ,
1170+ .vsync_end = 480 + 2 + 70 ,
1171+ .vtotal = 480 + 2 + 70 + 13 ,
1172+
1173+ .width_mm = 72 ,
1174+ .height_mm = 70 ,
1175+
1176+ .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC ,
1177+
1178+ .type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED ,
1179+ };
1180+
1181+ static const struct st7701_panel_desc wf40eswaa6mnn0_desc = {
1182+ .mode = & wf40eswaa6mnn0_mode ,
1183+ .lanes = 2 ,
1184+ .format = MIPI_DSI_FMT_RGB888 ,
1185+ .panel_sleep_delay = 0 ,
1186+
1187+ .pv_gamma = {
1188+ CFIELD_PREP (ST7701_CMD2_BK0_GAMCTRL_AJ_MASK , 0 ) |
1189+ CFIELD_PREP (ST7701_CMD2_BK0_GAMCTRL_VC0_MASK , 0x1 ),
1190+ CFIELD_PREP (ST7701_CMD2_BK0_GAMCTRL_AJ_MASK , 0 ) |
1191+ CFIELD_PREP (ST7701_CMD2_BK0_GAMCTRL_VC4_MASK , 0x08 ),
1192+ CFIELD_PREP (ST7701_CMD2_BK0_GAMCTRL_AJ_MASK , 0 ) |
1193+ CFIELD_PREP (ST7701_CMD2_BK0_GAMCTRL_VC8_MASK , 0x10 ),
1194+ CFIELD_PREP (ST7701_CMD2_BK0_GAMCTRL_VC16_MASK , 0x0c ),
1195+
1196+ CFIELD_PREP (ST7701_CMD2_BK0_GAMCTRL_AJ_MASK , 0 ) |
1197+ CFIELD_PREP (ST7701_CMD2_BK0_GAMCTRL_VC24_MASK , 0x10 ),
1198+ CFIELD_PREP (ST7701_CMD2_BK0_GAMCTRL_VC52_MASK , 0x08 ),
1199+ CFIELD_PREP (ST7701_CMD2_BK0_GAMCTRL_VC80_MASK , 0x10 ),
1200+ CFIELD_PREP (ST7701_CMD2_BK0_GAMCTRL_VC108_MASK , 0x0c ),
1201+
1202+ CFIELD_PREP (ST7701_CMD2_BK0_GAMCTRL_VC147_MASK , 0x08 ),
1203+ CFIELD_PREP (ST7701_CMD2_BK0_GAMCTRL_VC175_MASK , 0x22 ),
1204+ CFIELD_PREP (ST7701_CMD2_BK0_GAMCTRL_VC203_MASK , 0x04 ),
1205+ CFIELD_PREP (ST7701_CMD2_BK0_GAMCTRL_AJ_MASK , 0 ) |
1206+ CFIELD_PREP (ST7701_CMD2_BK0_GAMCTRL_VC231_MASK , 0x14 ),
1207+
1208+ CFIELD_PREP (ST7701_CMD2_BK0_GAMCTRL_VC239_MASK , 0x12 ),
1209+ CFIELD_PREP (ST7701_CMD2_BK0_GAMCTRL_AJ_MASK , 0 ) |
1210+ CFIELD_PREP (ST7701_CMD2_BK0_GAMCTRL_VC247_MASK , 0xb3 ),
1211+ CFIELD_PREP (ST7701_CMD2_BK0_GAMCTRL_AJ_MASK , 0 ) |
1212+ CFIELD_PREP (ST7701_CMD2_BK0_GAMCTRL_VC251_MASK , 0x3a ),
1213+ CFIELD_PREP (ST7701_CMD2_BK0_GAMCTRL_AJ_MASK , 0 ) |
1214+ CFIELD_PREP (ST7701_CMD2_BK0_GAMCTRL_VC255_MASK , 0x1f )
1215+ },
1216+ .nv_gamma = {
1217+ CFIELD_PREP (ST7701_CMD2_BK0_GAMCTRL_AJ_MASK , 0 ) |
1218+ CFIELD_PREP (ST7701_CMD2_BK0_GAMCTRL_VC4_MASK , 0x13 ),
1219+ CFIELD_PREP (ST7701_CMD2_BK0_GAMCTRL_AJ_MASK , 0 ) |
1220+ CFIELD_PREP (ST7701_CMD2_BK0_GAMCTRL_VC4_MASK , 0x19 ),
1221+ CFIELD_PREP (ST7701_CMD2_BK0_GAMCTRL_AJ_MASK , 0 ) |
1222+ CFIELD_PREP (ST7701_CMD2_BK0_GAMCTRL_VC8_MASK , 0x1f ),
1223+ CFIELD_PREP (ST7701_CMD2_BK0_GAMCTRL_VC16_MASK , 0x0f ),
1224+
1225+ CFIELD_PREP (ST7701_CMD2_BK0_GAMCTRL_AJ_MASK , 0 ) |
1226+ CFIELD_PREP (ST7701_CMD2_BK0_GAMCTRL_VC24_MASK , 0x14 ),
1227+ CFIELD_PREP (ST7701_CMD2_BK0_GAMCTRL_VC52_MASK , 0x07 ),
1228+ CFIELD_PREP (ST7701_CMD2_BK0_GAMCTRL_VC80_MASK , 0x07 ),
1229+ CFIELD_PREP (ST7701_CMD2_BK0_GAMCTRL_VC108_MASK , 0x08 ),
1230+
1231+ CFIELD_PREP (ST7701_CMD2_BK0_GAMCTRL_VC147_MASK , 0x07 ),
1232+ CFIELD_PREP (ST7701_CMD2_BK0_GAMCTRL_VC175_MASK , 0x22 ),
1233+ CFIELD_PREP (ST7701_CMD2_BK0_GAMCTRL_VC203_MASK , 0x02 ),
1234+ CFIELD_PREP (ST7701_CMD2_BK0_GAMCTRL_AJ_MASK , 0 ) |
1235+ CFIELD_PREP (ST7701_CMD2_BK0_GAMCTRL_VC231_MASK , 0xf ),
1236+
1237+ CFIELD_PREP (ST7701_CMD2_BK0_GAMCTRL_VC239_MASK , 0x0f ),
1238+ CFIELD_PREP (ST7701_CMD2_BK0_GAMCTRL_AJ_MASK , 0 ) |
1239+ CFIELD_PREP (ST7701_CMD2_BK0_GAMCTRL_VC247_MASK , 0xa3 ),
1240+ CFIELD_PREP (ST7701_CMD2_BK0_GAMCTRL_AJ_MASK , 0 ) |
1241+ CFIELD_PREP (ST7701_CMD2_BK0_GAMCTRL_VC251_MASK , 0x29 ),
1242+ CFIELD_PREP (ST7701_CMD2_BK0_GAMCTRL_AJ_MASK , 0 ) |
1243+ CFIELD_PREP (ST7701_CMD2_BK0_GAMCTRL_VC255_MASK , 0x0d )
1244+ },
1245+ .nlinv = 3 ,
1246+ .vop_uv = 4737500 ,
1247+ .vcom_uv = 662500 ,
1248+ .vgh_mv = 15000 ,
1249+ .vgl_mv = -10170 ,
1250+ .avdd_mv = 6600 ,
1251+ .avcl_mv = -4600 ,
1252+ .gamma_op_bias = OP_BIAS_MIDDLE ,
1253+ .input_op_bias = OP_BIAS_MIDDLE ,
1254+ .output_op_bias = OP_BIAS_MIN ,
1255+ .t2d_ns = 1600 ,
1256+ .t3d_ns = 10400 ,
1257+ .eot_en = true,
1258+ .gip_sequence = wf40eswaa6mnn0_gip_sequence ,
1259+ };
1260+
11381261static void st7701_cleanup (void * data )
11391262{
11401263 struct st7701 * st7701 = (struct st7701 * )data ;
@@ -1265,6 +1388,7 @@ static const struct of_device_id st7701_dsi_of_match[] = {
12651388 { .compatible = "densitron,dmt028vghmcmi-1a" , .data = & dmt028vghmcmi_1a_desc },
12661389 { .compatible = "elida,kd50t048a" , .data = & kd50t048a_desc },
12671390 { .compatible = "techstar,ts8550b" , .data = & ts8550b_desc },
1391+ { .compatible = "winstar,wf40eswaa6mnn0" , .data = & wf40eswaa6mnn0_desc },
12681392 { }
12691393};
12701394MODULE_DEVICE_TABLE (of , st7701_dsi_of_match );
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