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Shashank Babu Chinta Venkatakwilczynski
Shashank Babu Chinta Venkata
authored and
kwilczynski
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PCI: qcom: Add RX lane margining settings for 16.0 GT/s
Add RX lane margining settings for 16.0 GT/s (GEN 4) data rate. These settings improve link stability while operating at high date rates and helps to improve signal quality. Link: https://lore.kernel.org/linux-pci/20240911-pci-qcom-gen4-stability-v7-4-743f5c1fd027@linaro.org Tested-by: Johan Hovold <johan+linaro@kernel.org> Signed-off-by: Shashank Babu Chinta Venkata <quic_schintav@quicinc.com> [mani: dropped the code refactoring and minor changes] Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> [kwilczynski: commit log] Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org> Reviewed-by: Johan Hovold <johan+linaro@kernel.org> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
1 parent d45736b commit d14bc28

5 files changed

Lines changed: 56 additions & 2 deletions

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‎drivers/pci/controller/dwc/pcie-designware.h‎

Lines changed: 18 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -210,6 +210,24 @@
210210

211211
#define PCIE_PL_CHK_REG_ERR_ADDR 0xB28
212212

213+
/*
214+
* 16.0 GT/s (Gen 4) lane margining register definitions
215+
*/
216+
#define GEN4_LANE_MARGINING_1_OFF 0xB80
217+
#define MARGINING_MAX_VOLTAGE_OFFSET GENMASK(29, 24)
218+
#define MARGINING_NUM_VOLTAGE_STEPS GENMASK(22, 16)
219+
#define MARGINING_MAX_TIMING_OFFSET GENMASK(13, 8)
220+
#define MARGINING_NUM_TIMING_STEPS GENMASK(5, 0)
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222+
#define GEN4_LANE_MARGINING_2_OFF 0xB84
223+
#define MARGINING_IND_ERROR_SAMPLER BIT(28)
224+
#define MARGINING_SAMPLE_REPORTING_METHOD BIT(27)
225+
#define MARGINING_IND_LEFT_RIGHT_TIMING BIT(26)
226+
#define MARGINING_IND_UP_DOWN_VOLTAGE BIT(25)
227+
#define MARGINING_VOLTAGE_SUPPORTED BIT(24)
228+
#define MARGINING_MAXLANES GENMASK(20, 16)
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#define MARGINING_SAMPLE_RATE_TIMING GENMASK(13, 8)
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#define MARGINING_SAMPLE_RATE_VOLTAGE GENMASK(5, 0)
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/*
214232
* iATU Unroll-specific register definitions
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* From 4.80 core version the address translation will be made by unroll

‎drivers/pci/controller/dwc/pcie-qcom-common.c‎

Lines changed: 31 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -45,3 +45,34 @@ void qcom_pcie_common_set_16gt_equalization(struct dw_pcie *pci)
4545
dw_pcie_writel_dbi(pci, GEN3_EQ_CONTROL_OFF, reg);
4646
}
4747
EXPORT_SYMBOL_GPL(qcom_pcie_common_set_16gt_equalization);
48+
49+
void qcom_pcie_common_set_16gt_lane_margining(struct dw_pcie *pci)
50+
{
51+
u32 reg;
52+
53+
reg = dw_pcie_readl_dbi(pci, GEN4_LANE_MARGINING_1_OFF);
54+
reg &= ~(MARGINING_MAX_VOLTAGE_OFFSET |
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MARGINING_NUM_VOLTAGE_STEPS |
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MARGINING_MAX_TIMING_OFFSET |
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MARGINING_NUM_TIMING_STEPS);
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reg |= FIELD_PREP(MARGINING_MAX_VOLTAGE_OFFSET, 0x24) |
59+
FIELD_PREP(MARGINING_NUM_VOLTAGE_STEPS, 0x78) |
60+
FIELD_PREP(MARGINING_MAX_TIMING_OFFSET, 0x32) |
61+
FIELD_PREP(MARGINING_NUM_TIMING_STEPS, 0x10);
62+
dw_pcie_writel_dbi(pci, GEN4_LANE_MARGINING_1_OFF, reg);
63+
64+
reg = dw_pcie_readl_dbi(pci, GEN4_LANE_MARGINING_2_OFF);
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reg |= MARGINING_IND_ERROR_SAMPLER |
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MARGINING_SAMPLE_REPORTING_METHOD |
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MARGINING_IND_LEFT_RIGHT_TIMING |
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MARGINING_VOLTAGE_SUPPORTED;
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reg &= ~(MARGINING_IND_UP_DOWN_VOLTAGE |
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MARGINING_MAXLANES |
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MARGINING_SAMPLE_RATE_TIMING |
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MARGINING_SAMPLE_RATE_VOLTAGE);
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reg |= FIELD_PREP(MARGINING_MAXLANES, pci->num_lanes) |
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FIELD_PREP(MARGINING_SAMPLE_RATE_TIMING, 0x3f) |
75+
FIELD_PREP(MARGINING_SAMPLE_RATE_VOLTAGE, 0x3f);
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dw_pcie_writel_dbi(pci, GEN4_LANE_MARGINING_2_OFF, reg);
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}
78+
EXPORT_SYMBOL_GPL(qcom_pcie_common_set_16gt_lane_margining);

‎drivers/pci/controller/dwc/pcie-qcom-common.h‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -9,5 +9,6 @@
99
struct dw_pcie;
1010

1111
void qcom_pcie_common_set_16gt_equalization(struct dw_pcie *pci);
12+
void qcom_pcie_common_set_16gt_lane_margining(struct dw_pcie *pci);
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1314
#endif

‎drivers/pci/controller/dwc/pcie-qcom-ep.c‎

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -487,8 +487,10 @@ static int qcom_pcie_perst_deassert(struct dw_pcie *pci)
487487
goto err_disable_resources;
488488
}
489489

490-
if (pcie_link_speed[pci->max_link_speed] == PCIE_SPEED_16_0GT)
490+
if (pcie_link_speed[pci->max_link_speed] == PCIE_SPEED_16_0GT) {
491491
qcom_pcie_common_set_16gt_equalization(pci);
492+
qcom_pcie_common_set_16gt_lane_margining(pci);
493+
}
492494

493495
/*
494496
* The physical address of the MMIO region which is exposed as the BAR

‎drivers/pci/controller/dwc/pcie-qcom.c‎

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -296,8 +296,10 @@ static int qcom_pcie_start_link(struct dw_pcie *pci)
296296
{
297297
struct qcom_pcie *pcie = to_qcom_pcie(pci);
298298

299-
if (pcie_link_speed[pci->max_link_speed] == PCIE_SPEED_16_0GT)
299+
if (pcie_link_speed[pci->max_link_speed] == PCIE_SPEED_16_0GT) {
300300
qcom_pcie_common_set_16gt_equalization(pci);
301+
qcom_pcie_common_set_16gt_lane_margining(pci);
302+
}
301303

302304
/* Enable Link Training state machine */
303305
if (pcie->cfg->ops->ltssm_enable)

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