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Aurabindo Pillaialexdeucher
Aurabindo Pillai
authored and
alexdeucher
committed
drm/amd/display: add DCN301 specific logic for OTG programming
[Why&How] DCN301 does not have FAMS hence the workaround needed on other DCN3x variants related to OTG min/max selector programming is not applicable for it. Hence isolate it and have it use the old sequence without workaround. Fixes: 1598fc5 ("drm/amd/display: Program OTG vtotal min/max selectors unconditionally for DCN1+") Reviewed-by: Swapnil Patel <swapnil.patel@amd.com> Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Tested-by: Guilherme G. Piccoli <gpiccoli@igalia.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
1 parent 2ed5a4c commit d179250

4 files changed

Lines changed: 225 additions & 3 deletions

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‎drivers/gpu/drm/amd/display/dc/dcn301/Makefile‎

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@@ -11,7 +11,8 @@
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# Makefile for dcn30.
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DCN301 = dcn301_init.o dcn301_resource.o dcn301_dccg.o \
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dcn301_dio_link_encoder.o dcn301_hwseq.o dcn301_panel_cntl.o dcn301_hubbub.o
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dcn301_dio_link_encoder.o dcn301_hwseq.o dcn301_panel_cntl.o dcn301_hubbub.o \
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dcn301_optc.o
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AMD_DAL_DCN301 = $(addprefix $(AMDDALPATH)/dc/dcn301/,$(DCN301))
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‎drivers/gpu/drm/amd/display/dc/dcn301/dcn301_optc.c‎

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/*
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* Copyright 2020 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#include "reg_helper.h"
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#include "dcn301_optc.h"
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#include "dc.h"
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#include "dcn_calc_math.h"
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#include "dc_dmub_srv.h"
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#include "dml/dcn30/dcn30_fpu.h"
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#include "dc_trace.h"
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#define REG(reg)\
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optc1->tg_regs->reg
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#define CTX \
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optc1->base.ctx
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#undef FN
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#define FN(reg_name, field_name) \
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optc1->tg_shift->field_name, optc1->tg_mask->field_name
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/**
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* optc301_set_drr() - Program dynamic refresh rate registers m_OTGx_OTG_V_TOTAL_*.
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*
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* @optc: timing_generator instance.
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* @params: parameters used for Dynamic Refresh Rate.
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*/
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void optc301_set_drr(
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struct timing_generator *optc,
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const struct drr_params *params)
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{
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struct optc *optc1 = DCN10TG_FROM_TG(optc);
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if (params != NULL &&
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params->vertical_total_max > 0 &&
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params->vertical_total_min > 0) {
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if (params->vertical_total_mid != 0) {
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REG_SET(OTG_V_TOTAL_MID, 0,
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OTG_V_TOTAL_MID, params->vertical_total_mid - 1);
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REG_UPDATE_2(OTG_V_TOTAL_CONTROL,
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OTG_VTOTAL_MID_REPLACING_MAX_EN, 1,
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OTG_VTOTAL_MID_FRAME_NUM,
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(uint8_t)params->vertical_total_mid_frame_num);
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}
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optc->funcs->set_vtotal_min_max(optc, params->vertical_total_min - 1, params->vertical_total_max - 1);
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REG_UPDATE_5(OTG_V_TOTAL_CONTROL,
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OTG_V_TOTAL_MIN_SEL, 1,
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OTG_V_TOTAL_MAX_SEL, 1,
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OTG_FORCE_LOCK_ON_EVENT, 0,
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OTG_SET_V_TOTAL_MIN_MASK_EN, 0,
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OTG_SET_V_TOTAL_MIN_MASK, 0);
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// Setup manual flow control for EOF via TRIG_A
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optc->funcs->setup_manual_trigger(optc);
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} else {
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REG_UPDATE_4(OTG_V_TOTAL_CONTROL,
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OTG_SET_V_TOTAL_MIN_MASK, 0,
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OTG_V_TOTAL_MIN_SEL, 0,
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OTG_V_TOTAL_MAX_SEL, 0,
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OTG_FORCE_LOCK_ON_EVENT, 0);
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optc->funcs->set_vtotal_min_max(optc, 0, 0);
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}
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}
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void optc301_setup_manual_trigger(struct timing_generator *optc)
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{
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struct optc *optc1 = DCN10TG_FROM_TG(optc);
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REG_SET_8(OTG_TRIGA_CNTL, 0,
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OTG_TRIGA_SOURCE_SELECT, 21,
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OTG_TRIGA_SOURCE_PIPE_SELECT, optc->inst,
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OTG_TRIGA_RISING_EDGE_DETECT_CNTL, 1,
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OTG_TRIGA_FALLING_EDGE_DETECT_CNTL, 0,
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OTG_TRIGA_POLARITY_SELECT, 0,
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OTG_TRIGA_FREQUENCY_SELECT, 0,
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OTG_TRIGA_DELAY, 0,
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OTG_TRIGA_CLEAR, 1);
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}
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static struct timing_generator_funcs dcn30_tg_funcs = {
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.validate_timing = optc1_validate_timing,
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.program_timing = optc1_program_timing,
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.setup_vertical_interrupt0 = optc1_setup_vertical_interrupt0,
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.setup_vertical_interrupt1 = optc1_setup_vertical_interrupt1,
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.setup_vertical_interrupt2 = optc1_setup_vertical_interrupt2,
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.program_global_sync = optc1_program_global_sync,
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.enable_crtc = optc2_enable_crtc,
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.disable_crtc = optc1_disable_crtc,
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/* used by enable_timing_synchronization. Not need for FPGA */
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.is_counter_moving = optc1_is_counter_moving,
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.get_position = optc1_get_position,
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.get_frame_count = optc1_get_vblank_counter,
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.get_scanoutpos = optc1_get_crtc_scanoutpos,
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.get_otg_active_size = optc1_get_otg_active_size,
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.set_early_control = optc1_set_early_control,
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/* used by enable_timing_synchronization. Not need for FPGA */
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.wait_for_state = optc1_wait_for_state,
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.set_blank_color = optc3_program_blank_color,
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.did_triggered_reset_occur = optc1_did_triggered_reset_occur,
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.triplebuffer_lock = optc3_triplebuffer_lock,
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.triplebuffer_unlock = optc2_triplebuffer_unlock,
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.enable_reset_trigger = optc1_enable_reset_trigger,
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.enable_crtc_reset = optc1_enable_crtc_reset,
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.disable_reset_trigger = optc1_disable_reset_trigger,
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.lock = optc3_lock,
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.unlock = optc1_unlock,
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.lock_doublebuffer_enable = optc3_lock_doublebuffer_enable,
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.lock_doublebuffer_disable = optc3_lock_doublebuffer_disable,
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.enable_optc_clock = optc1_enable_optc_clock,
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.set_drr = optc301_set_drr,
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.get_last_used_drr_vtotal = optc2_get_last_used_drr_vtotal,
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.set_vtotal_min_max = optc3_set_vtotal_min_max,
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.set_static_screen_control = optc1_set_static_screen_control,
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.program_stereo = optc1_program_stereo,
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.is_stereo_left_eye = optc1_is_stereo_left_eye,
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.tg_init = optc3_tg_init,
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.is_tg_enabled = optc1_is_tg_enabled,
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.is_optc_underflow_occurred = optc1_is_optc_underflow_occurred,
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.clear_optc_underflow = optc1_clear_optc_underflow,
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.setup_global_swap_lock = NULL,
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.get_crc = optc1_get_crc,
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.configure_crc = optc2_configure_crc,
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.set_dsc_config = optc3_set_dsc_config,
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.get_dsc_status = optc2_get_dsc_status,
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.set_dwb_source = NULL,
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.set_odm_bypass = optc3_set_odm_bypass,
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.set_odm_combine = optc3_set_odm_combine,
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.get_optc_source = optc2_get_optc_source,
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.set_out_mux = optc3_set_out_mux,
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.set_drr_trigger_window = optc3_set_drr_trigger_window,
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.set_vtotal_change_limit = optc3_set_vtotal_change_limit,
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.set_gsl = optc2_set_gsl,
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.set_gsl_source_select = optc2_set_gsl_source_select,
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.set_vtg_params = optc1_set_vtg_params,
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.program_manual_trigger = optc2_program_manual_trigger,
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.setup_manual_trigger = optc301_setup_manual_trigger,
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.get_hw_timing = optc1_get_hw_timing,
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.wait_drr_doublebuffer_pending_clear = optc3_wait_drr_doublebuffer_pending_clear,
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};
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void dcn301_timing_generator_init(struct optc *optc1)
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{
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optc1->base.funcs = &dcn30_tg_funcs;
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optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1;
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optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1;
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optc1->min_h_blank = 32;
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optc1->min_v_blank = 3;
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optc1->min_v_blank_interlace = 5;
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optc1->min_h_sync_width = 4;
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optc1->min_v_sync_width = 1;
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}

‎drivers/gpu/drm/amd/display/dc/dcn301/dcn301_optc.h‎

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/*
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* Copyright 2020 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
6+
* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
8+
* and/or sell copies of the Software, and to permit persons to whom the
9+
* Software is furnished to do so, subject to the following conditions:
10+
*
11+
* The above copyright notice and this permission notice shall be included in
12+
* all copies or substantial portions of the Software.
13+
*
14+
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15+
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16+
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17+
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18+
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19+
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20+
* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#ifndef __DC_OPTC_DCN301_H__
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#define __DC_OPTC_DCN301_H__
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#include "dcn20/dcn20_optc.h"
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#include "dcn30/dcn30_optc.h"
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void dcn301_timing_generator_init(struct optc *optc1);
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void optc301_setup_manual_trigger(struct timing_generator *optc);
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void optc301_set_drr(struct timing_generator *optc, const struct drr_params *params);
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#endif /* __DC_OPTC_DCN301_H__ */

‎drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c‎

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#include "dcn30/dcn30_hubp.h"
4343
#include "irq/dcn30/irq_service_dcn30.h"
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#include "dcn30/dcn30_dpp.h"
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#include "dcn30/dcn30_optc.h"
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#include "dcn301/dcn301_optc.h"
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#include "dcn20/dcn20_hwseq.h"
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#include "dcn30/dcn30_hwseq.h"
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#include "dce110/dce110_hw_sequencer.h"
@@ -855,7 +855,7 @@ static struct timing_generator *dcn301_timing_generator_create(
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tgn10->tg_shift = &optc_shift;
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tgn10->tg_mask = &optc_mask;
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dcn30_timing_generator_init(tgn10);
858+
dcn301_timing_generator_init(tgn10);
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return &tgn10->base;
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}

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