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Dillon Varonealexdeucher
Dillon Varone
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alexdeucher
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drm/amd/display: Isolate dcn401 SMU functions
[WHY&HOW] SMU interfaces are not backwards and forwards compatible, so they should be isolated per version. Reviewed-by: Alvin Lee <alvin.lee2@amd.com> Signed-off-by: Dillon Varone <Dillon.Varone@amd.com> Signed-off-by: Ivan Lipski <ivan.lipski@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
1 parent b65cf4b commit d19f570

3 files changed

Lines changed: 140 additions & 14 deletions

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‎drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c‎

Lines changed: 13 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -162,7 +162,7 @@ static void dcn401_init_single_clock(struct clk_mgr_internal *clk_mgr, PPCLK_e c
162162
unsigned int i;
163163
char *entry_i = (char *)entry_0;
164164

165-
uint32_t ret = dcn30_smu_get_dpm_freq_by_index(clk_mgr, clk, 0xFF);
165+
uint32_t ret = dcn401_smu_get_dpm_freq_by_index(clk_mgr, clk, 0xFF);
166166

167167
if (ret & (1 << 31))
168168
/* fine-grained, only min and max */
@@ -174,7 +174,7 @@ static void dcn401_init_single_clock(struct clk_mgr_internal *clk_mgr, PPCLK_e c
174174

175175
/* if the initial message failed, num_levels will be 0 */
176176
for (i = 0; i < *num_levels && i < ARRAY_SIZE(clk_mgr->base.bw_params->clk_table.entries); i++) {
177-
*((unsigned int *)entry_i) = (dcn30_smu_get_dpm_freq_by_index(clk_mgr, clk, i) & 0xFFFF);
177+
*((unsigned int *)entry_i) = (dcn401_smu_get_dpm_freq_by_index(clk_mgr, clk, i) & 0xFFFF);
178178
entry_i += sizeof(clk_mgr->base.bw_params->clk_table.entries[0]);
179179
}
180180
}
@@ -231,20 +231,20 @@ void dcn401_init_clocks(struct clk_mgr *clk_mgr_base)
231231
clk_mgr->smu_present = false;
232232
clk_mgr->dpm_present = false;
233233

234-
if (!clk_mgr_base->force_smu_not_present && dcn30_smu_get_smu_version(clk_mgr, &clk_mgr->smu_ver))
234+
if (!clk_mgr_base->force_smu_not_present && dcn401_smu_get_smu_version(clk_mgr, &clk_mgr->smu_ver))
235235
clk_mgr->smu_present = true;
236236

237237
if (!clk_mgr->smu_present)
238238
return;
239239

240-
dcn30_smu_check_driver_if_version(clk_mgr);
241-
dcn30_smu_check_msg_header_version(clk_mgr);
240+
dcn401_smu_check_driver_if_version(clk_mgr);
241+
dcn401_smu_check_msg_header_version(clk_mgr);
242242

243243
/* DCFCLK */
244244
dcn401_init_single_clock(clk_mgr, PPCLK_DCFCLK,
245245
&clk_mgr_base->bw_params->clk_table.entries[0].dcfclk_mhz,
246246
&num_entries_per_clk->num_dcfclk_levels);
247-
clk_mgr_base->bw_params->dc_mode_limit.dcfclk_mhz = dcn30_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_DCFCLK);
247+
clk_mgr_base->bw_params->dc_mode_limit.dcfclk_mhz = dcn401_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_DCFCLK);
248248
if (num_entries_per_clk->num_dcfclk_levels && clk_mgr_base->bw_params->dc_mode_limit.dcfclk_mhz ==
249249
clk_mgr_base->bw_params->clk_table.entries[num_entries_per_clk->num_dcfclk_levels - 1].dcfclk_mhz)
250250
clk_mgr_base->bw_params->dc_mode_limit.dcfclk_mhz = 0;
@@ -253,7 +253,7 @@ void dcn401_init_clocks(struct clk_mgr *clk_mgr_base)
253253
dcn401_init_single_clock(clk_mgr, PPCLK_SOCCLK,
254254
&clk_mgr_base->bw_params->clk_table.entries[0].socclk_mhz,
255255
&num_entries_per_clk->num_socclk_levels);
256-
clk_mgr_base->bw_params->dc_mode_limit.socclk_mhz = dcn30_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_SOCCLK);
256+
clk_mgr_base->bw_params->dc_mode_limit.socclk_mhz = dcn401_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_SOCCLK);
257257
if (num_entries_per_clk->num_socclk_levels && clk_mgr_base->bw_params->dc_mode_limit.socclk_mhz ==
258258
clk_mgr_base->bw_params->clk_table.entries[num_entries_per_clk->num_socclk_levels - 1].socclk_mhz)
259259
clk_mgr_base->bw_params->dc_mode_limit.socclk_mhz = 0;
@@ -263,7 +263,7 @@ void dcn401_init_clocks(struct clk_mgr *clk_mgr_base)
263263
dcn401_init_single_clock(clk_mgr, PPCLK_DTBCLK,
264264
&clk_mgr_base->bw_params->clk_table.entries[0].dtbclk_mhz,
265265
&num_entries_per_clk->num_dtbclk_levels);
266-
clk_mgr_base->bw_params->dc_mode_limit.dtbclk_mhz = dcn30_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_DTBCLK);
266+
clk_mgr_base->bw_params->dc_mode_limit.dtbclk_mhz = dcn401_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_DTBCLK);
267267
if (num_entries_per_clk->num_dtbclk_levels && clk_mgr_base->bw_params->dc_mode_limit.dtbclk_mhz ==
268268
clk_mgr_base->bw_params->clk_table.entries[num_entries_per_clk->num_dtbclk_levels - 1].dtbclk_mhz)
269269
clk_mgr_base->bw_params->dc_mode_limit.dtbclk_mhz = 0;
@@ -273,7 +273,7 @@ void dcn401_init_clocks(struct clk_mgr *clk_mgr_base)
273273
dcn401_init_single_clock(clk_mgr, PPCLK_DISPCLK,
274274
&clk_mgr_base->bw_params->clk_table.entries[0].dispclk_mhz,
275275
&num_entries_per_clk->num_dispclk_levels);
276-
clk_mgr_base->bw_params->dc_mode_limit.dispclk_mhz = dcn30_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_DISPCLK);
276+
clk_mgr_base->bw_params->dc_mode_limit.dispclk_mhz = dcn401_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_DISPCLK);
277277
if (num_entries_per_clk->num_dispclk_levels && clk_mgr_base->bw_params->dc_mode_limit.dispclk_mhz ==
278278
clk_mgr_base->bw_params->clk_table.entries[num_entries_per_clk->num_dispclk_levels - 1].dispclk_mhz)
279279
clk_mgr_base->bw_params->dc_mode_limit.dispclk_mhz = 0;
@@ -1318,8 +1318,8 @@ static void dcn401_notify_wm_ranges(struct clk_mgr *clk_mgr_base)
13181318
table->Watermarks.WatermarkRow[i].WmSetting = i;
13191319
table->Watermarks.WatermarkRow[i].Flags = clk_mgr->base.bw_params->wm_table.nv_entries[i].pmfw_breakdown.wm_type;
13201320
}
1321-
dcn30_smu_set_dram_addr_high(clk_mgr, clk_mgr->wm_range_table_addr >> 32);
1322-
dcn30_smu_set_dram_addr_low(clk_mgr, clk_mgr->wm_range_table_addr & 0xFFFFFFFF);
1321+
dcn401_smu_set_dram_addr_high(clk_mgr, clk_mgr->wm_range_table_addr >> 32);
1322+
dcn401_smu_set_dram_addr_low(clk_mgr, clk_mgr->wm_range_table_addr & 0xFFFFFFFF);
13231323
dcn401_smu_transfer_wm_table_dram_2_smu(clk_mgr);
13241324
}
13251325

@@ -1390,7 +1390,7 @@ static void dcn401_get_memclk_states_from_smu(struct clk_mgr *clk_mgr_base)
13901390
clk_mgr_base->bw_params->clk_table.entries[num_entries_per_clk->num_memclk_levels - 1].memclk_mhz;
13911391
}
13921392

1393-
clk_mgr_base->bw_params->dc_mode_limit.memclk_mhz = dcn30_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_UCLK);
1393+
clk_mgr_base->bw_params->dc_mode_limit.memclk_mhz = dcn401_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_UCLK);
13941394
if (num_entries_per_clk->num_memclk_levels && clk_mgr_base->bw_params->dc_mode_limit.memclk_mhz ==
13951395
clk_mgr_base->bw_params->clk_table.entries[num_entries_per_clk->num_memclk_levels - 1].memclk_mhz)
13961396
clk_mgr_base->bw_params->dc_mode_limit.memclk_mhz = 0;
@@ -1399,7 +1399,7 @@ static void dcn401_get_memclk_states_from_smu(struct clk_mgr *clk_mgr_base)
13991399
dcn401_init_single_clock(clk_mgr, PPCLK_FCLK,
14001400
&clk_mgr_base->bw_params->clk_table.entries[0].fclk_mhz,
14011401
&num_entries_per_clk->num_fclk_levels);
1402-
clk_mgr_base->bw_params->dc_mode_limit.fclk_mhz = dcn30_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_FCLK);
1402+
clk_mgr_base->bw_params->dc_mode_limit.fclk_mhz = dcn401_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_FCLK);
14031403
if (num_entries_per_clk->num_fclk_levels && clk_mgr_base->bw_params->dc_mode_limit.fclk_mhz ==
14041404
clk_mgr_base->bw_params->clk_table.entries[num_entries_per_clk->num_fclk_levels - 1].fclk_mhz)
14051405
clk_mgr_base->bw_params->dc_mode_limit.fclk_mhz = 0;

‎drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c‎

Lines changed: 118 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -139,6 +139,59 @@ static bool dcn401_smu_send_msg_with_param_delay(struct clk_mgr_internal *clk_mg
139139
return false;
140140
}
141141

142+
bool dcn401_smu_get_smu_version(struct clk_mgr_internal *clk_mgr, unsigned int *version)
143+
{
144+
smu_print("SMU Get SMU version\n");
145+
146+
if (dcn401_smu_send_msg_with_param(clk_mgr,
147+
DALSMC_MSG_GetSmuVersion, 0, version)) {
148+
149+
smu_print("SMU version: %d\n", *version);
150+
151+
return true;
152+
}
153+
154+
return false;
155+
}
156+
157+
/* Message output should match SMU11_DRIVER_IF_VERSION in smu11_driver_if.h */
158+
bool dcn401_smu_check_driver_if_version(struct clk_mgr_internal *clk_mgr)
159+
{
160+
uint32_t response = 0;
161+
162+
smu_print("SMU Check driver if version\n");
163+
164+
if (dcn401_smu_send_msg_with_param(clk_mgr,
165+
DALSMC_MSG_GetDriverIfVersion, 0, &response)) {
166+
167+
smu_print("SMU driver if version: %d\n", response);
168+
169+
if (response == SMU14_DRIVER_IF_VERSION)
170+
return true;
171+
}
172+
173+
return false;
174+
}
175+
176+
/* Message output should match DALSMC_VERSION in dalsmc.h */
177+
bool dcn401_smu_check_msg_header_version(struct clk_mgr_internal *clk_mgr)
178+
{
179+
uint32_t response = 0;
180+
181+
smu_print("SMU Check msg header version\n");
182+
183+
if (dcn401_smu_send_msg_with_param(clk_mgr,
184+
DALSMC_MSG_GetMsgHeaderVersion, 0, &response)) {
185+
186+
smu_print("SMU msg header version: %d\n", response);
187+
188+
if (response == DALSMC_VERSION)
189+
return true;
190+
}
191+
192+
return false;
193+
}
194+
142195
void dcn401_smu_send_fclk_pstate_message(struct clk_mgr_internal *clk_mgr, bool support)
143196
{
144197
smu_print("FCLK P-state support value is : %d\n", support);
@@ -163,6 +216,22 @@ void dcn401_smu_send_cab_for_uclk_message(struct clk_mgr_internal *clk_mgr, unsi
163216
smu_print("Numways for SubVP : %d\n", num_ways);
164217
}
165218

219+
void dcn401_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t addr_high)
220+
{
221+
smu_print("SMU Set DRAM addr high: %d\n", addr_high);
222+
223+
dcn401_smu_send_msg_with_param(clk_mgr,
224+
DALSMC_MSG_SetDalDramAddrHigh, addr_high, NULL);
225+
}
226+
227+
void dcn401_smu_set_dram_addr_low(struct clk_mgr_internal *clk_mgr, uint32_t addr_low)
228+
{
229+
smu_print("SMU Set DRAM addr low: %d\n", addr_low);
230+
231+
dcn401_smu_send_msg_with_param(clk_mgr,
232+
DALSMC_MSG_SetDalDramAddrLow, addr_low, NULL);
233+
}
234+
166235
void dcn401_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr)
167236
{
168237
smu_print("SMU Transfer WM table DRAM 2 SMU\n");
@@ -348,3 +417,52 @@ unsigned int dcn401_smu_get_num_of_umc_channels(struct clk_mgr_internal *clk_mgr
348417

349418
return response;
350419
}
420+
421+
/*
422+
* Frequency in MHz returned in lower 16 bits for valid DPM level
423+
*
424+
* Call with dpm_level = 0xFF to query features, return value will be:
425+
* Bits 7:0 - number of DPM levels
426+
* Bit 28 - 1 = auto DPM on
427+
* Bit 29 - 1 = sweep DPM on
428+
* Bit 30 - 1 = forced DPM on
429+
* Bit 31 - 0 = discrete, 1 = fine-grained
430+
*
431+
* With fine-grained DPM, only min and max frequencies will be reported
432+
*
433+
* Returns 0 on failure
434+
*/
435+
unsigned int dcn401_smu_get_dpm_freq_by_index(struct clk_mgr_internal *clk_mgr, uint32_t clk, uint8_t dpm_level)
436+
{
437+
uint32_t response = 0;
438+
439+
/* bits 23:16 for clock type, lower 8 bits for DPM level */
440+
uint32_t param = (clk << 16) | dpm_level;
441+
442+
smu_print("SMU Get dpm freq by index: clk = %d, dpm_level = %d\n", clk, dpm_level);
443+
444+
dcn401_smu_send_msg_with_param(clk_mgr,
445+
DALSMC_MSG_GetDpmFreqByIndex, param, &response);
446+
447+
smu_print("SMU dpm freq: %d MHz\n", response);
448+
449+
return response;
450+
}
451+
452+
/* Returns the max DPM frequency in DC mode in MHz, 0 on failure */
453+
unsigned int dcn401_smu_get_dc_mode_max_dpm_freq(struct clk_mgr_internal *clk_mgr, uint32_t clk)
454+
{
455+
uint32_t response = 0;
456+
457+
/* bits 23:16 for clock type */
458+
uint32_t param = clk << 16;
459+
460+
smu_print("SMU Get DC mode max DPM freq: clk = %d\n", clk);
461+
462+
dcn401_smu_send_msg_with_param(clk_mgr,
463+
DALSMC_MSG_GetDcModeMaxDpmFreq, param, &response);
464+
465+
smu_print("SMU DC mode max DMP freq: %d MHz\n", response);
466+
467+
return response;
468+
}

‎drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.h‎

Lines changed: 9 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -7,11 +7,17 @@
77

88
#include "os_types.h"
99
#include "core_types.h"
10-
#include "dcn32/dcn32_clk_mgr_smu_msg.h"
1110

11+
struct clk_mgr_internal;
12+
13+
bool dcn401_smu_get_smu_version(struct clk_mgr_internal *clk_mgr, unsigned int *version);
14+
bool dcn401_smu_check_driver_if_version(struct clk_mgr_internal *clk_mgr);
15+
bool dcn401_smu_check_msg_header_version(struct clk_mgr_internal *clk_mgr);
1216
void dcn401_smu_send_fclk_pstate_message(struct clk_mgr_internal *clk_mgr, bool support);
1317
void dcn401_smu_send_uclk_pstate_message(struct clk_mgr_internal *clk_mgr, bool support);
1418
void dcn401_smu_send_cab_for_uclk_message(struct clk_mgr_internal *clk_mgr, unsigned int num_ways);
19+
void dcn401_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t addr_high);
20+
void dcn401_smu_set_dram_addr_low(struct clk_mgr_internal *clk_mgr, uint32_t addr_low);
1521
void dcn401_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr);
1622
void dcn401_smu_set_pme_workaround(struct clk_mgr_internal *clk_mgr);
1723
unsigned int dcn401_smu_set_hard_min_by_freq(struct clk_mgr_internal *clk_mgr, uint32_t clk, uint16_t freq_mhz);
@@ -29,5 +35,7 @@ bool dcn401_smu_set_subvp_uclk_fclk_hardmin(struct clk_mgr_internal *clk_mgr,
2935
void dcn401_smu_set_min_deep_sleep_dcef_clk(struct clk_mgr_internal *clk_mgr, uint32_t freq_mhz);
3036
void dcn401_smu_set_num_of_displays(struct clk_mgr_internal *clk_mgr, uint32_t num_displays);
3137
unsigned int dcn401_smu_get_num_of_umc_channels(struct clk_mgr_internal *clk_mgr);
38+
unsigned int dcn401_smu_get_dc_mode_max_dpm_freq(struct clk_mgr_internal *clk_mgr, uint32_t clk);
39+
unsigned int dcn401_smu_get_dpm_freq_by_index(struct clk_mgr_internal *clk_mgr, uint32_t clk, uint8_t dpm_level);
3240

3341
#endif /* __DCN401_CLK_MGR_SMU_MSG_H_ */

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