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zhang-ruirafaeljw
zhang-rui
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rafaeljw
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intel_idle: Add AlderLake support
Similar to SPR, the C1 and C1E states on ADL are mutually exclusive. Only one of them can be enabled at a time. But contrast to SPR, which usually has a strong latency requirement as a Xeon processor, C1E is preferred on ADL for better energy efficiency. Add custom C-state tables for ADL with both C1 and C1E, and 1. Enable the "C1E promotion" bit in MSR_IA32_POWER_CTL and mark C1 with the CPUIDLE_FLAG_UNUSABLE flag, so C1 is not available by default. 2. Add support for the "preferred_cstates" module parameter, so that users can choose to use C1 instead of C1E by booting with "intel_idle.preferred_cstates=2". Separate custom C-state tables are introduced for the ADL mobile and desktop processors, because of the exit latency differences between these two variants, especially with respect to PC10. Signed-off-by: Zhang Rui <rui.zhang@intel.com> [ rjw: Changelog edits, code rearrangement ] Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
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‎drivers/idle/intel_idle.c‎

Lines changed: 133 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -764,6 +764,106 @@ static struct cpuidle_state icx_cstates[] __initdata = {
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.enter = NULL }
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};
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/*
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* On AlderLake C1 has to be disabled if C1E is enabled, and vice versa.
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* C1E is enabled only if "C1E promotion" bit is set in MSR_IA32_POWER_CTL.
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* But in this case there is effectively no C1, because C1 requests are
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* promoted to C1E. If the "C1E promotion" bit is cleared, then both C1
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* and C1E requests end up with C1, so there is effectively no C1E.
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*
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* By default we enable C1E and disable C1 by marking it with
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* 'CPUIDLE_FLAG_UNUSABLE'.
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*/
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static struct cpuidle_state adl_cstates[] __initdata = {
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{
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.name = "C1",
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.desc = "MWAIT 0x00",
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.flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_UNUSABLE,
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.exit_latency = 1,
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.target_residency = 1,
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.enter = &intel_idle,
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.enter_s2idle = intel_idle_s2idle, },
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{
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.name = "C1E",
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.desc = "MWAIT 0x01",
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.flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
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.exit_latency = 2,
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.target_residency = 4,
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.enter = &intel_idle,
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.enter_s2idle = intel_idle_s2idle, },
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{
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.name = "C6",
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.desc = "MWAIT 0x20",
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.flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
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.exit_latency = 220,
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.target_residency = 600,
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.enter = &intel_idle,
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.enter_s2idle = intel_idle_s2idle, },
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{
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.name = "C8",
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.desc = "MWAIT 0x40",
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.flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TLB_FLUSHED,
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.exit_latency = 280,
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.target_residency = 800,
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.enter = &intel_idle,
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.enter_s2idle = intel_idle_s2idle, },
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{
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.name = "C10",
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.desc = "MWAIT 0x60",
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.flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
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.exit_latency = 680,
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.target_residency = 2000,
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.enter = &intel_idle,
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.enter_s2idle = intel_idle_s2idle, },
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{
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.enter = NULL }
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};
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static struct cpuidle_state adl_l_cstates[] __initdata = {
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{
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.name = "C1",
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.desc = "MWAIT 0x00",
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.flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_UNUSABLE,
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.exit_latency = 1,
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.target_residency = 1,
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.enter = &intel_idle,
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.enter_s2idle = intel_idle_s2idle, },
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{
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.name = "C1E",
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.desc = "MWAIT 0x01",
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.flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
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.exit_latency = 2,
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.target_residency = 4,
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.enter = &intel_idle,
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.enter_s2idle = intel_idle_s2idle, },
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{
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.name = "C6",
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.desc = "MWAIT 0x20",
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.flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
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.exit_latency = 170,
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.target_residency = 500,
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.enter = &intel_idle,
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.enter_s2idle = intel_idle_s2idle, },
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{
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.name = "C8",
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.desc = "MWAIT 0x40",
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.flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TLB_FLUSHED,
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.exit_latency = 200,
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.target_residency = 600,
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.enter = &intel_idle,
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.enter_s2idle = intel_idle_s2idle, },
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{
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.name = "C10",
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.desc = "MWAIT 0x60",
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.flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
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.exit_latency = 230,
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.target_residency = 700,
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.enter = &intel_idle,
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.enter_s2idle = intel_idle_s2idle, },
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{
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.enter = NULL }
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};
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/*
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* On Sapphire Rapids Xeon C1 has to be disabled if C1E is enabled, and vice
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* versa. On SPR C1E is enabled only if "C1E promotion" bit is set in
@@ -1147,6 +1247,14 @@ static const struct idle_cpu idle_cpu_icx __initconst = {
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.use_acpi = true,
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};
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static const struct idle_cpu idle_cpu_adl __initconst = {
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.state_table = adl_cstates,
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};
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static const struct idle_cpu idle_cpu_adl_l __initconst = {
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.state_table = adl_l_cstates,
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};
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static const struct idle_cpu idle_cpu_spr __initconst = {
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.state_table = spr_cstates,
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.disable_promotion_to_c1e = true,
@@ -1215,6 +1323,8 @@ static const struct x86_cpu_id intel_idle_ids[] __initconst = {
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X86_MATCH_INTEL_FAM6_MODEL(SKYLAKE_X, &idle_cpu_skx),
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X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_X, &idle_cpu_icx),
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X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_D, &idle_cpu_icx),
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X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE, &idle_cpu_adl),
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X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_L, &idle_cpu_adl_l),
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X86_MATCH_INTEL_FAM6_MODEL(SAPPHIRERAPIDS_X, &idle_cpu_spr),
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X86_MATCH_INTEL_FAM6_MODEL(XEON_PHI_KNL, &idle_cpu_knl),
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X86_MATCH_INTEL_FAM6_MODEL(XEON_PHI_KNM, &idle_cpu_knl),
@@ -1573,6 +1683,25 @@ static void __init skx_idle_state_table_update(void)
15731683
}
15741684
}
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/**
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* adl_idle_state_table_update - Adjust AlderLake idle states table.
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*/
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static void __init adl_idle_state_table_update(void)
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{
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/* Check if user prefers C1 over C1E. */
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if (preferred_states_mask & BIT(1) && !(preferred_states_mask & BIT(2))) {
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cpuidle_state_table[0].flags &= ~CPUIDLE_FLAG_UNUSABLE;
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cpuidle_state_table[1].flags |= CPUIDLE_FLAG_UNUSABLE;
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/* Disable C1E by clearing the "C1E promotion" bit. */
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c1e_promotion = C1E_PROMOTION_DISABLE;
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return;
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}
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/* Make sure C1E is enabled by default */
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c1e_promotion = C1E_PROMOTION_ENABLE;
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}
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/**
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* spr_idle_state_table_update - Adjust Sapphire Rapids idle states table.
15781707
*/
@@ -1642,6 +1771,10 @@ static void __init intel_idle_init_cstates_icpu(struct cpuidle_driver *drv)
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case INTEL_FAM6_SAPPHIRERAPIDS_X:
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spr_idle_state_table_update();
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break;
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case INTEL_FAM6_ALDERLAKE:
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case INTEL_FAM6_ALDERLAKE_L:
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adl_idle_state_table_update();
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break;
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}
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16471780
for (cstate = 0; cstate < CPUIDLE_STATE_MAX; ++cstate) {

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