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Anna ManiscalcoRob Clark
Anna Maniscalco
authored and
Rob Clark
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drm/msm: Fix a7xx per pipe register programming
GEN7_GRAS_NC_MODE_CNTL was only programmed for BR and not for BV pipe but it needs to be programmed for both. Program both pipes in hw_init and introducea separate reglist for it in order to add this register to the dynamic reglist which supports restoring registers per pipe. Fixes: 91389b4 ("drm/msm/a6xx: Add a pwrup_list field to a6xx_info") Cc: stable@vger.kernel.org Reviewed-by: Akhil P Oommen <akhilpo@oss.qualcomm.com> Signed-off-by: Anna Maniscalco <anna.maniscalco2000@gmail.com> Patchwork: https://patchwork.freedesktop.org/patch/691553/ Message-ID: <20251201-gras_nc_mode_fix-v3-1-92a8a10d91d0@gmail.com> Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
1 parent 6c6915b commit d2b6e71

4 files changed

Lines changed: 55 additions & 5 deletions

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‎drivers/gpu/drm/msm/adreno/a6xx_catalog.c‎

Lines changed: 11 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1376,7 +1376,6 @@ static const uint32_t a7xx_pwrup_reglist_regs[] = {
13761376
REG_A6XX_UCHE_MODE_CNTL,
13771377
REG_A6XX_RB_NC_MODE_CNTL,
13781378
REG_A6XX_RB_CMP_DBG_ECO_CNTL,
1379-
REG_A7XX_GRAS_NC_MODE_CNTL,
13801379
REG_A6XX_RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE_ENABLE,
13811380
REG_A6XX_UCHE_GBIF_GX_CONFIG,
13821381
REG_A6XX_UCHE_CLIENT_PF,
@@ -1449,6 +1448,12 @@ static const u32 a750_ifpc_reglist_regs[] = {
14491448

14501449
DECLARE_ADRENO_REGLIST_LIST(a750_ifpc_reglist);
14511450

1451+
static const struct adreno_reglist_pipe a7xx_dyn_pwrup_reglist_regs[] = {
1452+
{ REG_A7XX_GRAS_NC_MODE_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) },
1453+
};
1454+
1455+
DECLARE_ADRENO_REGLIST_PIPE_LIST(a7xx_dyn_pwrup_reglist);
1456+
14521457
static const struct adreno_info a7xx_gpus[] = {
14531458
{
14541459
.chip_ids = ADRENO_CHIP_IDS(0x07000200),
@@ -1492,6 +1497,7 @@ static const struct adreno_info a7xx_gpus[] = {
14921497
.hwcg = a730_hwcg,
14931498
.protect = &a730_protect,
14941499
.pwrup_reglist = &a7xx_pwrup_reglist,
1500+
.dyn_pwrup_reglist = &a7xx_dyn_pwrup_reglist,
14951501
.gbif_cx = a640_gbif,
14961502
.gmu_cgc_mode = 0x00020000,
14971503
},
@@ -1514,6 +1520,7 @@ static const struct adreno_info a7xx_gpus[] = {
15141520
.hwcg = a740_hwcg,
15151521
.protect = &a730_protect,
15161522
.pwrup_reglist = &a7xx_pwrup_reglist,
1523+
.dyn_pwrup_reglist = &a7xx_dyn_pwrup_reglist,
15171524
.gbif_cx = a640_gbif,
15181525
.gmu_chipid = 0x7020100,
15191526
.gmu_cgc_mode = 0x00020202,
@@ -1548,6 +1555,7 @@ static const struct adreno_info a7xx_gpus[] = {
15481555
.hwcg = a740_hwcg,
15491556
.protect = &a730_protect,
15501557
.pwrup_reglist = &a7xx_pwrup_reglist,
1558+
.dyn_pwrup_reglist = &a7xx_dyn_pwrup_reglist,
15511559
.ifpc_reglist = &a750_ifpc_reglist,
15521560
.gbif_cx = a640_gbif,
15531561
.gmu_chipid = 0x7050001,
@@ -1590,6 +1598,7 @@ static const struct adreno_info a7xx_gpus[] = {
15901598
.a6xx = &(const struct a6xx_info) {
15911599
.protect = &a730_protect,
15921600
.pwrup_reglist = &a7xx_pwrup_reglist,
1601+
.dyn_pwrup_reglist = &a7xx_dyn_pwrup_reglist,
15931602
.ifpc_reglist = &a750_ifpc_reglist,
15941603
.gbif_cx = a640_gbif,
15951604
.gmu_chipid = 0x7090100,
@@ -1624,6 +1633,7 @@ static const struct adreno_info a7xx_gpus[] = {
16241633
.hwcg = a740_hwcg,
16251634
.protect = &a730_protect,
16261635
.pwrup_reglist = &a7xx_pwrup_reglist,
1636+
.dyn_pwrup_reglist = &a7xx_dyn_pwrup_reglist,
16271637
.gbif_cx = a640_gbif,
16281638
.gmu_chipid = 0x70f0000,
16291639
.gmu_cgc_mode = 0x00020222,

‎drivers/gpu/drm/msm/adreno/a6xx_gpu.c‎

Lines changed: 30 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -849,9 +849,16 @@ static void a6xx_set_ubwc_config(struct msm_gpu *gpu)
849849
min_acc_len_64b << 3 |
850850
hbb_lo << 1 | ubwc_mode);
851851

852-
if (adreno_is_a7xx(adreno_gpu))
853-
gpu_write(gpu, REG_A7XX_GRAS_NC_MODE_CNTL,
854-
FIELD_PREP(GENMASK(8, 5), hbb_lo));
852+
if (adreno_is_a7xx(adreno_gpu)) {
853+
for (u32 pipe_id = PIPE_BR; pipe_id <= PIPE_BV; pipe_id++) {
854+
gpu_write(gpu, REG_A7XX_CP_APERTURE_CNTL_HOST,
855+
A7XX_CP_APERTURE_CNTL_HOST_PIPE(pipe_id));
856+
gpu_write(gpu, REG_A7XX_GRAS_NC_MODE_CNTL,
857+
FIELD_PREP(GENMASK(8, 5), hbb_lo));
858+
}
859+
gpu_write(gpu, REG_A7XX_CP_APERTURE_CNTL_HOST,
860+
A7XX_CP_APERTURE_CNTL_HOST_PIPE(PIPE_NONE));
861+
}
855862

856863
gpu_write(gpu, REG_A6XX_UCHE_MODE_CNTL,
857864
min_acc_len_64b << 23 | hbb_lo << 21);
@@ -865,9 +872,11 @@ static void a7xx_patch_pwrup_reglist(struct msm_gpu *gpu)
865872
struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
866873
struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
867874
const struct adreno_reglist_list *reglist;
875+
const struct adreno_reglist_pipe_list *dyn_pwrup_reglist;
868876
void *ptr = a6xx_gpu->pwrup_reglist_ptr;
869877
struct cpu_gpu_lock *lock = ptr;
870878
u32 *dest = (u32 *)&lock->regs[0];
879+
u32 dyn_pwrup_reglist_count = 0;
871880
int i;
872881

873882
lock->gpu_req = lock->cpu_req = lock->turn = 0;
@@ -909,7 +918,24 @@ static void a7xx_patch_pwrup_reglist(struct msm_gpu *gpu)
909918
* (<aperture, shifted 12 bits> <address> <data>), and the length is
910919
* stored as number for triplets in dynamic_list_len.
911920
*/
912-
lock->dynamic_list_len = 0;
921+
dyn_pwrup_reglist = adreno_gpu->info->a6xx->dyn_pwrup_reglist;
922+
if (dyn_pwrup_reglist) {
923+
for (u32 pipe_id = PIPE_BR; pipe_id <= PIPE_BV; pipe_id++) {
924+
gpu_write(gpu, REG_A7XX_CP_APERTURE_CNTL_HOST,
925+
A7XX_CP_APERTURE_CNTL_HOST_PIPE(pipe_id));
926+
for (i = 0; i < dyn_pwrup_reglist->count; i++) {
927+
if ((dyn_pwrup_reglist->regs[i].pipe & BIT(pipe_id)) == 0)
928+
continue;
929+
*dest++ = A7XX_CP_APERTURE_CNTL_HOST_PIPE(pipe_id);
930+
*dest++ = dyn_pwrup_reglist->regs[i].offset;
931+
*dest++ = gpu_read(gpu, dyn_pwrup_reglist->regs[i].offset);
932+
dyn_pwrup_reglist_count++;
933+
}
934+
}
935+
gpu_write(gpu, REG_A7XX_CP_APERTURE_CNTL_HOST,
936+
A7XX_CP_APERTURE_CNTL_HOST_PIPE(PIPE_NONE));
937+
}
938+
lock->dynamic_list_len = dyn_pwrup_reglist_count;
913939
}
914940

915941
static int a7xx_preempt_start(struct msm_gpu *gpu)

‎drivers/gpu/drm/msm/adreno/a6xx_gpu.h‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -45,6 +45,7 @@ struct a6xx_info {
4545
const struct adreno_reglist *hwcg;
4646
const struct adreno_protect *protect;
4747
const struct adreno_reglist_list *pwrup_reglist;
48+
const struct adreno_reglist_pipe_list *dyn_pwrup_reglist;
4849
const struct adreno_reglist_list *ifpc_reglist;
4950
const struct adreno_reglist *gbif_cx;
5051
const struct adreno_reglist_pipe *nonctxt_reglist;

‎drivers/gpu/drm/msm/adreno/adreno_gpu.h‎

Lines changed: 13 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -188,6 +188,19 @@ static const struct adreno_reglist_list name = { \
188188
.count = ARRAY_SIZE(name ## _regs), \
189189
};
190190

191+
struct adreno_reglist_pipe_list {
192+
/** @reg: List of register **/
193+
const struct adreno_reglist_pipe *regs;
194+
/** @count: Number of registers in the list **/
195+
u32 count;
196+
};
197+
198+
#define DECLARE_ADRENO_REGLIST_PIPE_LIST(name) \
199+
static const struct adreno_reglist_pipe_list name = { \
200+
.regs = name ## _regs, \
201+
.count = ARRAY_SIZE(name ## _regs), \
202+
};
203+
191204
struct adreno_gpu {
192205
struct msm_gpu base;
193206
const struct adreno_info *info;

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