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Dapeng MiPeter Zijlstra
Dapeng Mi
authored and
Peter Zijlstra
committed
perf/x86/intel: Add core PMU support for DMR
This patch enables core PMU features for Diamond Rapids (Panther Cove microarchitecture), including Panther Cove specific counter and PEBS constraints, a new cache events ID table, and the model-specific OMR events extra registers table. For detailed information about counter constraints, please refer to section 16.3 "COUNTER RESTRICTIONS" in the ISE documentation. Signed-off-by: Dapeng Mi <dapeng1.mi@linux.intel.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Link: https://patch.msgid.link/20260114011750.350569-4-dapeng1.mi@linux.intel.com
1 parent d2bdcde commit d345b6b

3 files changed

Lines changed: 207 additions & 1 deletion

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‎arch/x86/events/intel/core.c‎

Lines changed: 178 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -435,6 +435,62 @@ static struct extra_reg intel_lnc_extra_regs[] __read_mostly = {
435435
EVENT_EXTRA_END
436436
};
437437

438+
static struct event_constraint intel_pnc_event_constraints[] = {
439+
FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
440+
FIXED_EVENT_CONSTRAINT(0x0100, 0), /* INST_RETIRED.PREC_DIST */
441+
FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
442+
FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
443+
FIXED_EVENT_CONSTRAINT(0x013c, 2), /* CPU_CLK_UNHALTED.REF_TSC_P */
444+
FIXED_EVENT_CONSTRAINT(0x0400, 3), /* SLOTS */
445+
METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_RETIRING, 0),
446+
METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BAD_SPEC, 1),
447+
METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FE_BOUND, 2),
448+
METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BE_BOUND, 3),
449+
METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_HEAVY_OPS, 4),
450+
METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BR_MISPREDICT, 5),
451+
METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FETCH_LAT, 6),
452+
METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_MEM_BOUND, 7),
453+
454+
INTEL_EVENT_CONSTRAINT(0x20, 0xf),
455+
INTEL_EVENT_CONSTRAINT(0x79, 0xf),
456+
457+
INTEL_UEVENT_CONSTRAINT(0x0275, 0xf),
458+
INTEL_UEVENT_CONSTRAINT(0x0176, 0xf),
459+
INTEL_UEVENT_CONSTRAINT(0x04a4, 0x1),
460+
INTEL_UEVENT_CONSTRAINT(0x08a4, 0x1),
461+
INTEL_UEVENT_CONSTRAINT(0x01cd, 0xfc),
462+
INTEL_UEVENT_CONSTRAINT(0x02cd, 0x3),
463+
464+
INTEL_EVENT_CONSTRAINT(0xd0, 0xf),
465+
INTEL_EVENT_CONSTRAINT(0xd1, 0xf),
466+
INTEL_EVENT_CONSTRAINT(0xd4, 0xf),
467+
INTEL_EVENT_CONSTRAINT(0xd6, 0xf),
468+
INTEL_EVENT_CONSTRAINT(0xdf, 0xf),
469+
INTEL_EVENT_CONSTRAINT(0xce, 0x1),
470+
471+
INTEL_UEVENT_CONSTRAINT(0x01b1, 0x8),
472+
INTEL_UEVENT_CONSTRAINT(0x0847, 0xf),
473+
INTEL_UEVENT_CONSTRAINT(0x0446, 0xf),
474+
INTEL_UEVENT_CONSTRAINT(0x0846, 0xf),
475+
INTEL_UEVENT_CONSTRAINT(0x0148, 0xf),
476+
477+
EVENT_CONSTRAINT_END
478+
};
479+
480+
static struct extra_reg intel_pnc_extra_regs[] __read_mostly = {
481+
/* must define OMR_X first, see intel_alt_er() */
482+
INTEL_UEVENT_EXTRA_REG(0x012a, MSR_OMR_0, 0x40ffffff0000ffffull, OMR_0),
483+
INTEL_UEVENT_EXTRA_REG(0x022a, MSR_OMR_1, 0x40ffffff0000ffffull, OMR_1),
484+
INTEL_UEVENT_EXTRA_REG(0x042a, MSR_OMR_2, 0x40ffffff0000ffffull, OMR_2),
485+
INTEL_UEVENT_EXTRA_REG(0x082a, MSR_OMR_3, 0x40ffffff0000ffffull, OMR_3),
486+
INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
487+
INTEL_UEVENT_EXTRA_REG(0x02c6, MSR_PEBS_FRONTEND, 0x9, FE),
488+
INTEL_UEVENT_EXTRA_REG(0x03c6, MSR_PEBS_FRONTEND, 0x7fff1f, FE),
489+
INTEL_UEVENT_EXTRA_REG(0x40ad, MSR_PEBS_FRONTEND, 0xf, FE),
490+
INTEL_UEVENT_EXTRA_REG(0x04c2, MSR_PEBS_FRONTEND, 0x8, FE),
491+
EVENT_EXTRA_END
492+
};
493+
438494
EVENT_ATTR_STR(mem-loads, mem_ld_nhm, "event=0x0b,umask=0x10,ldlat=3");
439495
EVENT_ATTR_STR(mem-loads, mem_ld_snb, "event=0xcd,umask=0x1,ldlat=3");
440496
EVENT_ATTR_STR(mem-stores, mem_st_snb, "event=0xcd,umask=0x2");
@@ -650,6 +706,102 @@ static __initconst const u64 glc_hw_cache_extra_regs
650706
},
651707
};
652708

709+
static __initconst const u64 pnc_hw_cache_event_ids
710+
[PERF_COUNT_HW_CACHE_MAX]
711+
[PERF_COUNT_HW_CACHE_OP_MAX]
712+
[PERF_COUNT_HW_CACHE_RESULT_MAX] =
713+
{
714+
[ C(L1D ) ] = {
715+
[ C(OP_READ) ] = {
716+
[ C(RESULT_ACCESS) ] = 0x81d0,
717+
[ C(RESULT_MISS) ] = 0xe124,
718+
},
719+
[ C(OP_WRITE) ] = {
720+
[ C(RESULT_ACCESS) ] = 0x82d0,
721+
},
722+
},
723+
[ C(L1I ) ] = {
724+
[ C(OP_READ) ] = {
725+
[ C(RESULT_MISS) ] = 0xe424,
726+
},
727+
[ C(OP_WRITE) ] = {
728+
[ C(RESULT_ACCESS) ] = -1,
729+
[ C(RESULT_MISS) ] = -1,
730+
},
731+
},
732+
[ C(LL ) ] = {
733+
[ C(OP_READ) ] = {
734+
[ C(RESULT_ACCESS) ] = 0x12a,
735+
[ C(RESULT_MISS) ] = 0x12a,
736+
},
737+
[ C(OP_WRITE) ] = {
738+
[ C(RESULT_ACCESS) ] = 0x12a,
739+
[ C(RESULT_MISS) ] = 0x12a,
740+
},
741+
},
742+
[ C(DTLB) ] = {
743+
[ C(OP_READ) ] = {
744+
[ C(RESULT_ACCESS) ] = 0x81d0,
745+
[ C(RESULT_MISS) ] = 0xe12,
746+
},
747+
[ C(OP_WRITE) ] = {
748+
[ C(RESULT_ACCESS) ] = 0x82d0,
749+
[ C(RESULT_MISS) ] = 0xe13,
750+
},
751+
},
752+
[ C(ITLB) ] = {
753+
[ C(OP_READ) ] = {
754+
[ C(RESULT_ACCESS) ] = -1,
755+
[ C(RESULT_MISS) ] = 0xe11,
756+
},
757+
[ C(OP_WRITE) ] = {
758+
[ C(RESULT_ACCESS) ] = -1,
759+
[ C(RESULT_MISS) ] = -1,
760+
},
761+
[ C(OP_PREFETCH) ] = {
762+
[ C(RESULT_ACCESS) ] = -1,
763+
[ C(RESULT_MISS) ] = -1,
764+
},
765+
},
766+
[ C(BPU ) ] = {
767+
[ C(OP_READ) ] = {
768+
[ C(RESULT_ACCESS) ] = 0x4c4,
769+
[ C(RESULT_MISS) ] = 0x4c5,
770+
},
771+
[ C(OP_WRITE) ] = {
772+
[ C(RESULT_ACCESS) ] = -1,
773+
[ C(RESULT_MISS) ] = -1,
774+
},
775+
[ C(OP_PREFETCH) ] = {
776+
[ C(RESULT_ACCESS) ] = -1,
777+
[ C(RESULT_MISS) ] = -1,
778+
},
779+
},
780+
[ C(NODE) ] = {
781+
[ C(OP_READ) ] = {
782+
[ C(RESULT_ACCESS) ] = -1,
783+
[ C(RESULT_MISS) ] = -1,
784+
},
785+
},
786+
};
787+
788+
static __initconst const u64 pnc_hw_cache_extra_regs
789+
[PERF_COUNT_HW_CACHE_MAX]
790+
[PERF_COUNT_HW_CACHE_OP_MAX]
791+
[PERF_COUNT_HW_CACHE_RESULT_MAX] =
792+
{
793+
[ C(LL ) ] = {
794+
[ C(OP_READ) ] = {
795+
[ C(RESULT_ACCESS) ] = 0x4000000000000001,
796+
[ C(RESULT_MISS) ] = 0xFFFFF000000001,
797+
},
798+
[ C(OP_WRITE) ] = {
799+
[ C(RESULT_ACCESS) ] = 0x4000000000000002,
800+
[ C(RESULT_MISS) ] = 0xFFFFF000000002,
801+
},
802+
},
803+
};
804+
653805
/*
654806
* Notes on the events:
655807
* - data reads do not include code reads (comparable to earlier tables)
@@ -7236,6 +7388,20 @@ static __always_inline void intel_pmu_init_lnc(struct pmu *pmu)
72367388
hybrid(pmu, extra_regs) = intel_lnc_extra_regs;
72377389
}
72387390

7391+
static __always_inline void intel_pmu_init_pnc(struct pmu *pmu)
7392+
{
7393+
intel_pmu_init_glc(pmu);
7394+
x86_pmu.flags &= ~PMU_FL_HAS_RSP_1;
7395+
x86_pmu.flags |= PMU_FL_HAS_OMR;
7396+
memcpy(hybrid_var(pmu, hw_cache_event_ids),
7397+
pnc_hw_cache_event_ids, sizeof(hw_cache_event_ids));
7398+
memcpy(hybrid_var(pmu, hw_cache_extra_regs),
7399+
pnc_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
7400+
hybrid(pmu, event_constraints) = intel_pnc_event_constraints;
7401+
hybrid(pmu, pebs_constraints) = intel_pnc_pebs_event_constraints;
7402+
hybrid(pmu, extra_regs) = intel_pnc_extra_regs;
7403+
}
7404+
72397405
static __always_inline void intel_pmu_init_skt(struct pmu *pmu)
72407406
{
72417407
intel_pmu_init_grt(pmu);
@@ -7897,9 +8063,21 @@ __init int intel_pmu_init(void)
78978063
x86_pmu.extra_regs = intel_rwc_extra_regs;
78988064
pr_cont("Granite Rapids events, ");
78998065
name = "granite_rapids";
8066+
goto glc_common;
8067+
8068+
case INTEL_DIAMONDRAPIDS_X:
8069+
intel_pmu_init_pnc(NULL);
8070+
x86_pmu.pebs_latency_data = pnc_latency_data;
8071+
8072+
pr_cont("Panthercove events, ");
8073+
name = "panthercove";
8074+
goto glc_base;
79008075

79018076
glc_common:
79028077
intel_pmu_init_glc(NULL);
8078+
intel_pmu_pebs_data_source_skl(true);
8079+
8080+
glc_base:
79038081
x86_pmu.pebs_ept = 1;
79048082
x86_pmu.hw_config = hsw_hw_config;
79058083
x86_pmu.get_event_constraints = glc_get_event_constraints;
@@ -7909,7 +8087,6 @@ __init int intel_pmu_init(void)
79098087
mem_attr = glc_events_attrs;
79108088
td_attr = glc_td_events_attrs;
79118089
tsx_attr = glc_tsx_events_attrs;
7912-
intel_pmu_pebs_data_source_skl(true);
79138090
break;
79148091

79158092
case INTEL_ALDERLAKE:

‎arch/x86/events/intel/ds.c‎

Lines changed: 27 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1425,6 +1425,33 @@ struct event_constraint intel_lnc_pebs_event_constraints[] = {
14251425
EVENT_CONSTRAINT_END
14261426
};
14271427

1428+
struct event_constraint intel_pnc_pebs_event_constraints[] = {
1429+
INTEL_FLAGS_UEVENT_CONSTRAINT(0x100, 0x100000000ULL), /* INST_RETIRED.PREC_DIST */
1430+
INTEL_FLAGS_UEVENT_CONSTRAINT(0x0400, 0x800000000ULL),
1431+
1432+
INTEL_HYBRID_LDLAT_CONSTRAINT(0x1cd, 0xfc),
1433+
INTEL_HYBRID_STLAT_CONSTRAINT(0x2cd, 0x3),
1434+
INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x11d0, 0xf), /* MEM_INST_RETIRED.STLB_MISS_LOADS */
1435+
INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x12d0, 0xf), /* MEM_INST_RETIRED.STLB_MISS_STORES */
1436+
INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x21d0, 0xf), /* MEM_INST_RETIRED.LOCK_LOADS */
1437+
INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x41d0, 0xf), /* MEM_INST_RETIRED.SPLIT_LOADS */
1438+
INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x42d0, 0xf), /* MEM_INST_RETIRED.SPLIT_STORES */
1439+
INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x81d0, 0xf), /* MEM_INST_RETIRED.ALL_LOADS */
1440+
INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x82d0, 0xf), /* MEM_INST_RETIRED.ALL_STORES */
1441+
1442+
INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD_RANGE(0xd1, 0xd4, 0xf),
1443+
1444+
INTEL_FLAGS_EVENT_CONSTRAINT(0xd0, 0xf),
1445+
INTEL_FLAGS_EVENT_CONSTRAINT(0xd6, 0xf),
1446+
1447+
/*
1448+
* Everything else is handled by PMU_FL_PEBS_ALL, because we
1449+
* need the full constraints from the main table.
1450+
*/
1451+
1452+
EVENT_CONSTRAINT_END
1453+
};
1454+
14281455
struct event_constraint *intel_pebs_constraints(struct perf_event *event)
14291456
{
14301457
struct event_constraint *pebs_constraints = hybrid(event->pmu, pebs_constraints);

‎arch/x86/events/perf_event.h‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1698,6 +1698,8 @@ extern struct event_constraint intel_glc_pebs_event_constraints[];
16981698

16991699
extern struct event_constraint intel_lnc_pebs_event_constraints[];
17001700

1701+
extern struct event_constraint intel_pnc_pebs_event_constraints[];
1702+
17011703
struct event_constraint *intel_pebs_constraints(struct perf_event *event);
17021704

17031705
void intel_pmu_pebs_add(struct perf_event *event);

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