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Merge tag 'renesas-clk-for-v5.20-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas
Pull Renesas clk driver updates from Geert Uytterhoeven: - Add GPT/POEG (PWM) clocks and resets on RZ/G2L - Add PFC and WDT clocks and resets on RZ/V2M - Add thermal, SDHI, Z (CPU core), PCIe, and HSCIF (serial) clocks on R-Car S4-8 - Miscellaneous fixes and improvements * tag 'renesas-clk-for-v5.20-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: clk: renesas: r8a779f0: Add HSCIF clocks clk: renesas: r8a779f0: Add PCIe clocks clk: renesas: r8a779f0: Add Z0 and Z1 clock support dt-bindings: clock: renesas,rzg2l: Simplify header file references clk: renesas: rza1: Remove struct rz_cpg clk: renesas: r8a7779: Remove struct r8a7779_cpg clk: renesas: r8a7778: Remove struct r8a7778_cpg clk: renesas: sh73a0: Remove sh73a0_cpg.reg clk: renesas: r8a7740: Remove r8a7740_cpg.reg clk: renesas: r8a73a4: Remove r8a73a4_cpg.reg clk: renesas: r8a779f0: Add SDHI0 clock clk: renesas: r8a779f0: Add thermal clock clk: renesas: rzg2l: Fix reset status function clk: renesas: r9a06g032: Fix UART clkgrp bitsel clk: renesas: r9a06g032: Drop some unused fields clk: renesas: r9a09g011: Add WDT clock and reset entries clk: renesas: r9a09g011: Add PFC clock and reset entries clk: renesas: r9a07g044: Add POEG clock and reset entries clk: renesas: r9a07g044: Add GPT clock and reset entry
2 parents f2906aa + 080bcd8 commit d39afb7

12 files changed

Lines changed: 117 additions & 115 deletions

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‎Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml‎

Lines changed: 3 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -45,10 +45,9 @@ properties:
4545
description: |
4646
- For CPG core clocks, the two clock specifier cells must be "CPG_CORE"
4747
and a core clock reference, as defined in
48-
<dt-bindings/clock/r9a0*-cpg.h>
48+
<dt-bindings/clock/r9a0*-cpg.h>,
4949
- For module clocks, the two clock specifier cells must be "CPG_MOD" and
50-
a module number, as defined in the <dt-bindings/clock/r9a07g0*-cpg.h> or
51-
<dt-bindings/clock/r9a09g011-cpg.h>.
50+
a module number, as defined in <dt-bindings/clock/r9a0*-cpg.h>.
5251
const: 2
5352

5453
'#power-domain-cells':
@@ -62,7 +61,7 @@ properties:
6261
'#reset-cells':
6362
description:
6463
The single reset specifier cell must be the module number, as defined in
65-
the <dt-bindings/clock/r9a07g0*-cpg.h> or <dt-bindings/clock/r9a09g011-cpg.h>.
64+
<dt-bindings/clock/r9a0*-cpg.h>.
6665
const: 1
6766

6867
required:

‎drivers/clk/renesas/clk-r8a73a4.c‎

Lines changed: 11 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -18,7 +18,6 @@
1818
struct r8a73a4_cpg {
1919
struct clk_onecell_data data;
2020
spinlock_t lock;
21-
void __iomem *reg;
2221
};
2322

2423
#define CPG_CKSCR 0xc0
@@ -59,7 +58,7 @@ static const struct clk_div_table div4_div_table[] = {
5958

6059
static struct clk * __init
6160
r8a73a4_cpg_register_clock(struct device_node *np, struct r8a73a4_cpg *cpg,
62-
const char *name)
61+
void __iomem *base, const char *name)
6362
{
6463
const struct clk_div_table *table = NULL;
6564
const char *parent_name;
@@ -69,7 +68,7 @@ r8a73a4_cpg_register_clock(struct device_node *np, struct r8a73a4_cpg *cpg,
6968

7069

7170
if (!strcmp(name, "main")) {
72-
u32 ckscr = readl(cpg->reg + CPG_CKSCR);
71+
u32 ckscr = readl(base + CPG_CKSCR);
7372

7473
switch ((ckscr >> 28) & 3) {
7574
case 0: /* extal1 */
@@ -93,14 +92,14 @@ r8a73a4_cpg_register_clock(struct device_node *np, struct r8a73a4_cpg *cpg,
9392
* clock implementation and we currently have no need to change
9493
* the multiplier value.
9594
*/
96-
u32 value = readl(cpg->reg + CPG_PLL0CR);
95+
u32 value = readl(base + CPG_PLL0CR);
9796

9897
parent_name = "main";
9998
mult = ((value >> 24) & 0x7f) + 1;
10099
if (value & BIT(20))
101100
div = 2;
102101
} else if (!strcmp(name, "pll1")) {
103-
u32 value = readl(cpg->reg + CPG_PLL1CR);
102+
u32 value = readl(base + CPG_PLL1CR);
104103

105104
parent_name = "main";
106105
/* XXX: enable bit? */
@@ -123,7 +122,7 @@ r8a73a4_cpg_register_clock(struct device_node *np, struct r8a73a4_cpg *cpg,
123122
default:
124123
return ERR_PTR(-EINVAL);
125124
}
126-
value = readl(cpg->reg + cr);
125+
value = readl(base + cr);
127126
switch ((value >> 5) & 7) {
128127
case 0:
129128
parent_name = "main";
@@ -159,7 +158,7 @@ r8a73a4_cpg_register_clock(struct device_node *np, struct r8a73a4_cpg *cpg,
159158
shift = 0;
160159
}
161160
div *= 32;
162-
mult = 0x20 - ((readl(cpg->reg + CPG_FRQCRC) >> shift) & 0x1f);
161+
mult = 0x20 - ((readl(base + CPG_FRQCRC) >> shift) & 0x1f);
163162
} else {
164163
struct div4_clk *c;
165164

@@ -181,14 +180,15 @@ r8a73a4_cpg_register_clock(struct device_node *np, struct r8a73a4_cpg *cpg,
181180
mult, div);
182181
} else {
183182
return clk_register_divider_table(NULL, name, parent_name, 0,
184-
cpg->reg + reg, shift, 4, 0,
183+
base + reg, shift, 4, 0,
185184
table, &cpg->lock);
186185
}
187186
}
188187

189188
static void __init r8a73a4_cpg_clocks_init(struct device_node *np)
190189
{
191190
struct r8a73a4_cpg *cpg;
191+
void __iomem *base;
192192
struct clk **clks;
193193
unsigned int i;
194194
int num_clks;
@@ -213,8 +213,8 @@ static void __init r8a73a4_cpg_clocks_init(struct device_node *np)
213213
cpg->data.clks = clks;
214214
cpg->data.clk_num = num_clks;
215215

216-
cpg->reg = of_iomap(np, 0);
217-
if (WARN_ON(cpg->reg == NULL))
216+
base = of_iomap(np, 0);
217+
if (WARN_ON(base == NULL))
218218
return;
219219

220220
for (i = 0; i < num_clks; ++i) {
@@ -224,7 +224,7 @@ static void __init r8a73a4_cpg_clocks_init(struct device_node *np)
224224
of_property_read_string_index(np, "clock-output-names", i,
225225
&name);
226226

227-
clk = r8a73a4_cpg_register_clock(np, cpg, name);
227+
clk = r8a73a4_cpg_register_clock(np, cpg, base, name);
228228
if (IS_ERR(clk))
229229
pr_err("%s: failed to register %pOFn %s clock (%ld)\n",
230230
__func__, np, name, PTR_ERR(clk));

‎drivers/clk/renesas/clk-r8a7740.c‎

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -18,7 +18,6 @@
1818
struct r8a7740_cpg {
1919
struct clk_onecell_data data;
2020
spinlock_t lock;
21-
void __iomem *reg;
2221
};
2322

2423
#define CPG_FRQCRA 0x00
@@ -61,7 +60,7 @@ static u32 cpg_mode __initdata;
6160

6261
static struct clk * __init
6362
r8a7740_cpg_register_clock(struct device_node *np, struct r8a7740_cpg *cpg,
64-
const char *name)
63+
void __iomem *base, const char *name)
6564
{
6665
const struct clk_div_table *table = NULL;
6766
const char *parent_name;
@@ -96,20 +95,20 @@ r8a7740_cpg_register_clock(struct device_node *np, struct r8a7740_cpg *cpg,
9695
* clock implementation and we currently have no need to change
9796
* the multiplier value.
9897
*/
99-
u32 value = readl(cpg->reg + CPG_FRQCRC);
98+
u32 value = readl(base + CPG_FRQCRC);
10099
parent_name = "system";
101100
mult = ((value >> 24) & 0x7f) + 1;
102101
} else if (!strcmp(name, "pllc1")) {
103-
u32 value = readl(cpg->reg + CPG_FRQCRA);
102+
u32 value = readl(base + CPG_FRQCRA);
104103
parent_name = "system";
105104
mult = ((value >> 24) & 0x7f) + 1;
106105
div = 2;
107106
} else if (!strcmp(name, "pllc2")) {
108-
u32 value = readl(cpg->reg + CPG_PLLC2CR);
107+
u32 value = readl(base + CPG_PLLC2CR);
109108
parent_name = "system";
110109
mult = ((value >> 24) & 0x3f) + 1;
111110
} else if (!strcmp(name, "usb24s")) {
112-
u32 value = readl(cpg->reg + CPG_USBCKCR);
111+
u32 value = readl(base + CPG_USBCKCR);
113112
if (value & BIT(7))
114113
/* extal2 */
115114
parent_name = of_clk_get_parent_name(np, 1);
@@ -137,14 +136,15 @@ r8a7740_cpg_register_clock(struct device_node *np, struct r8a7740_cpg *cpg,
137136
mult, div);
138137
} else {
139138
return clk_register_divider_table(NULL, name, parent_name, 0,
140-
cpg->reg + reg, shift, 4, 0,
139+
base + reg, shift, 4, 0,
141140
table, &cpg->lock);
142141
}
143142
}
144143

145144
static void __init r8a7740_cpg_clocks_init(struct device_node *np)
146145
{
147146
struct r8a7740_cpg *cpg;
147+
void __iomem *base;
148148
struct clk **clks;
149149
unsigned int i;
150150
int num_clks;
@@ -172,8 +172,8 @@ static void __init r8a7740_cpg_clocks_init(struct device_node *np)
172172
cpg->data.clks = clks;
173173
cpg->data.clk_num = num_clks;
174174

175-
cpg->reg = of_iomap(np, 0);
176-
if (WARN_ON(cpg->reg == NULL))
175+
base = of_iomap(np, 0);
176+
if (WARN_ON(base == NULL))
177177
return;
178178

179179
for (i = 0; i < num_clks; ++i) {
@@ -183,7 +183,7 @@ static void __init r8a7740_cpg_clocks_init(struct device_node *np)
183183
of_property_read_string_index(np, "clock-output-names", i,
184184
&name);
185185

186-
clk = r8a7740_cpg_register_clock(np, cpg, name);
186+
clk = r8a7740_cpg_register_clock(np, cpg, base, name);
187187
if (IS_ERR(clk))
188188
pr_err("%s: failed to register %pOFn %s clock (%ld)\n",
189189
__func__, np, name, PTR_ERR(clk));

‎drivers/clk/renesas/clk-r8a7778.c‎

Lines changed: 9 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -11,12 +11,6 @@
1111
#include <linux/slab.h>
1212
#include <linux/soc/renesas/rcar-rst.h>
1313

14-
struct r8a7778_cpg {
15-
struct clk_onecell_data data;
16-
spinlock_t lock;
17-
void __iomem *reg;
18-
};
19-
2014
/* PLL multipliers per bits 11, 12, and 18 of MODEMR */
2115
static const struct {
2216
unsigned long plla_mult;
@@ -47,8 +41,7 @@ static u32 cpg_mode_rates __initdata;
4741
static u32 cpg_mode_divs __initdata;
4842

4943
static struct clk * __init
50-
r8a7778_cpg_register_clock(struct device_node *np, struct r8a7778_cpg *cpg,
51-
const char *name)
44+
r8a7778_cpg_register_clock(struct device_node *np, const char *name)
5245
{
5346
if (!strcmp(name, "plla")) {
5447
return clk_register_fixed_factor(NULL, "plla",
@@ -77,7 +70,7 @@ r8a7778_cpg_register_clock(struct device_node *np, struct r8a7778_cpg *cpg,
7770

7871
static void __init r8a7778_cpg_clocks_init(struct device_node *np)
7972
{
80-
struct r8a7778_cpg *cpg;
73+
struct clk_onecell_data *data;
8174
struct clk **clks;
8275
unsigned int i;
8376
int num_clks;
@@ -100,23 +93,17 @@ static void __init r8a7778_cpg_clocks_init(struct device_node *np)
10093
return;
10194
}
10295

103-
cpg = kzalloc(sizeof(*cpg), GFP_KERNEL);
96+
data = kzalloc(sizeof(*data), GFP_KERNEL);
10497
clks = kcalloc(num_clks, sizeof(*clks), GFP_KERNEL);
105-
if (cpg == NULL || clks == NULL) {
98+
if (data == NULL || clks == NULL) {
10699
/* We're leaking memory on purpose, there's no point in cleaning
107100
* up as the system won't boot anyway.
108101
*/
109102
return;
110103
}
111104

112-
spin_lock_init(&cpg->lock);
113-
114-
cpg->data.clks = clks;
115-
cpg->data.clk_num = num_clks;
116-
117-
cpg->reg = of_iomap(np, 0);
118-
if (WARN_ON(cpg->reg == NULL))
119-
return;
105+
data->clks = clks;
106+
data->clk_num = num_clks;
120107

121108
for (i = 0; i < num_clks; ++i) {
122109
const char *name;
@@ -125,15 +112,15 @@ static void __init r8a7778_cpg_clocks_init(struct device_node *np)
125112
of_property_read_string_index(np, "clock-output-names", i,
126113
&name);
127114

128-
clk = r8a7778_cpg_register_clock(np, cpg, name);
115+
clk = r8a7778_cpg_register_clock(np, name);
129116
if (IS_ERR(clk))
130117
pr_err("%s: failed to register %pOFn %s clock (%ld)\n",
131118
__func__, np, name, PTR_ERR(clk));
132119
else
133-
cpg->data.clks[i] = clk;
120+
data->clks[i] = clk;
134121
}
135122

136-
of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data);
123+
of_clk_add_provider(np, of_clk_src_onecell_get, data);
137124

138125
cpg_mstp_add_clk_domain(np);
139126
}

‎drivers/clk/renesas/clk-r8a7779.c‎

Lines changed: 9 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -21,12 +21,6 @@
2121

2222
#define CPG_NUM_CLOCKS (R8A7779_CLK_OUT + 1)
2323

24-
struct r8a7779_cpg {
25-
struct clk_onecell_data data;
26-
spinlock_t lock;
27-
void __iomem *reg;
28-
};
29-
3024
/* -----------------------------------------------------------------------------
3125
* CPG Clock Data
3226
*/
@@ -87,7 +81,7 @@ static const unsigned int cpg_plla_mult[4] __initconst = { 42, 48, 56, 64 };
8781
*/
8882

8983
static struct clk * __init
90-
r8a7779_cpg_register_clock(struct device_node *np, struct r8a7779_cpg *cpg,
84+
r8a7779_cpg_register_clock(struct device_node *np,
9185
const struct cpg_clk_config *config,
9286
unsigned int plla_mult, const char *name)
9387
{
@@ -119,7 +113,7 @@ r8a7779_cpg_register_clock(struct device_node *np, struct r8a7779_cpg *cpg,
119113
static void __init r8a7779_cpg_clocks_init(struct device_node *np)
120114
{
121115
const struct cpg_clk_config *config;
122-
struct r8a7779_cpg *cpg;
116+
struct clk_onecell_data *data;
123117
struct clk **clks;
124118
unsigned int i, plla_mult;
125119
int num_clks;
@@ -134,19 +128,17 @@ static void __init r8a7779_cpg_clocks_init(struct device_node *np)
134128
return;
135129
}
136130

137-
cpg = kzalloc(sizeof(*cpg), GFP_KERNEL);
131+
data = kzalloc(sizeof(*data), GFP_KERNEL);
138132
clks = kcalloc(CPG_NUM_CLOCKS, sizeof(*clks), GFP_KERNEL);
139-
if (cpg == NULL || clks == NULL) {
133+
if (data == NULL || clks == NULL) {
140134
/* We're leaking memory on purpose, there's no point in cleaning
141135
* up as the system won't boot anyway.
142136
*/
143137
return;
144138
}
145139

146-
spin_lock_init(&cpg->lock);
147-
148-
cpg->data.clks = clks;
149-
cpg->data.clk_num = num_clks;
140+
data->clks = clks;
141+
data->clk_num = num_clks;
150142

151143
config = &cpg_clk_configs[CPG_CLK_CONFIG_INDEX(mode)];
152144
plla_mult = cpg_plla_mult[CPG_PLLA_MULT_INDEX(mode)];
@@ -158,16 +150,15 @@ static void __init r8a7779_cpg_clocks_init(struct device_node *np)
158150
of_property_read_string_index(np, "clock-output-names", i,
159151
&name);
160152

161-
clk = r8a7779_cpg_register_clock(np, cpg, config,
162-
plla_mult, name);
153+
clk = r8a7779_cpg_register_clock(np, config, plla_mult, name);
163154
if (IS_ERR(clk))
164155
pr_err("%s: failed to register %pOFn %s clock (%ld)\n",
165156
__func__, np, name, PTR_ERR(clk));
166157
else
167-
cpg->data.clks[i] = clk;
158+
data->clks[i] = clk;
168159
}
169160

170-
of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data);
161+
of_clk_add_provider(np, of_clk_src_onecell_get, data);
171162

172163
cpg_mstp_add_clk_domain(np);
173164
}

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