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Merge tag 'riscv-dt-for-v6.4' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into soc/dt
RISC-V Devicetrees for v6.4 Microchip: A "fix" for the system controller's regs on PolarFire SoC, adding a missing reg property. The patch had been sitting there for months and I only re-found it recently, so you can guess how much of a "fix" it actually is. It'll become needed when the system controller's QSPI gets added in the future, but at present there's no urgency as the driver can handle both the current and "fixed" versions. StarFive: Basic support for the JH7110 & the associated first-party dev board, the VisionFive v2 (in two forms). There's a bunch of dt-bindings required for this too, all of which have had input from the DT folk. There's enough in this tag to boot to a console w/ an initramfs but little more. The SoC supports some of the "new" bit manipulation instructions, which is a good test for the recently added Zbb support in the kernel. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> * tag 'riscv-dt-for-v6.4' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux: riscv: dts: starfive: Add StarFive JH7110 VisionFive 2 board device tree riscv: dts: starfive: Add StarFive JH7110 pin function definitions riscv: dts: starfive: Add initial StarFive JH7110 device tree dt-bindings: riscv: Add SiFive S7 compatible dt-bindings: interrupt-controller: Add StarFive JH7110 plic dt-bindings: timer: Add StarFive JH7110 clint dt-bindings: clock: Add StarFive JH7110 always-on clock and reset generator dt-bindings: clock: Add StarFive JH7110 system clock and reset generator riscv: dts: microchip: fix the mpfs' mailbox regs riscv: dts: microchip: add mpfs specific macb reset support Link: https://lore.kernel.org/r/20230406-shank-impromptu-3d483bbc249f@spud Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2 parents acda89d + 4cd4beb commit d40a2f5

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‎Documentation/devicetree/bindings/clock/starfive,jh7110-aoncrg.yaml‎

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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/starfive,jh7110-aoncrg.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: StarFive JH7110 Always-On Clock and Reset Generator
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maintainers:
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- Emil Renner Berthing <kernel@esmil.dk>
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properties:
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compatible:
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const: starfive,jh7110-aoncrg
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reg:
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maxItems: 1
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clocks:
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oneOf:
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- items:
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- description: Main Oscillator (24 MHz)
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- description: GMAC0 RMII reference or GMAC0 RGMII RX
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- description: STG AXI/AHB
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- description: APB Bus
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- description: GMAC0 GTX
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- items:
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- description: Main Oscillator (24 MHz)
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- description: GMAC0 RMII reference or GMAC0 RGMII RX
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- description: STG AXI/AHB or GMAC0 RGMII RX
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- description: APB Bus or STG AXI/AHB
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- description: GMAC0 GTX or APB Bus
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- description: RTC Oscillator (32.768 kHz) or GMAC0 GTX
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- items:
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- description: Main Oscillator (24 MHz)
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- description: GMAC0 RMII reference
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- description: GMAC0 RGMII RX
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- description: STG AXI/AHB
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- description: APB Bus
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- description: GMAC0 GTX
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- description: RTC Oscillator (32.768 kHz)
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clock-names:
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oneOf:
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- minItems: 5
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items:
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- const: osc
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- enum:
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- gmac0_rmii_refin
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- gmac0_rgmii_rxin
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- const: stg_axiahb
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- const: apb_bus
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- const: gmac0_gtxclk
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- const: rtc_osc
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- minItems: 6
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items:
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- const: osc
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- const: gmac0_rmii_refin
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- const: gmac0_rgmii_rxin
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- const: stg_axiahb
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- const: apb_bus
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- const: gmac0_gtxclk
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- const: rtc_osc
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'#clock-cells':
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const: 1
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description:
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See <dt-bindings/clock/starfive,jh7110-crg.h> for valid indices.
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'#reset-cells':
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const: 1
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description:
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See <dt-bindings/reset/starfive,jh7110-crg.h> for valid indices.
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- '#clock-cells'
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- '#reset-cells'
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/starfive,jh7110-crg.h>
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clock-controller@17000000 {
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compatible = "starfive,jh7110-aoncrg";
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reg = <0x17000000 0x10000>;
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clocks = <&osc>, <&gmac0_rmii_refin>,
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<&gmac0_rgmii_rxin>,
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<&syscrg JH7110_SYSCLK_STG_AXIAHB>,
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<&syscrg JH7110_SYSCLK_APB_BUS>,
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<&syscrg JH7110_SYSCLK_GMAC0_GTXCLK>,
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<&rtc_osc>;
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clock-names = "osc", "gmac0_rmii_refin",
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"gmac0_rgmii_rxin", "stg_axiahb",
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"apb_bus", "gmac0_gtxclk",
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"rtc_osc";
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#clock-cells = <1>;
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#reset-cells = <1>;
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};

‎Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml‎

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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/starfive,jh7110-syscrg.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: StarFive JH7110 System Clock and Reset Generator
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maintainers:
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- Emil Renner Berthing <kernel@esmil.dk>
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properties:
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compatible:
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const: starfive,jh7110-syscrg
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reg:
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maxItems: 1
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clocks:
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oneOf:
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- items:
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- description: Main Oscillator (24 MHz)
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- description: GMAC1 RMII reference or GMAC1 RGMII RX
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- description: External I2S TX bit clock
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- description: External I2S TX left/right channel clock
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- description: External I2S RX bit clock
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- description: External I2S RX left/right channel clock
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- description: External TDM clock
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- description: External audio master clock
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- items:
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- description: Main Oscillator (24 MHz)
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- description: GMAC1 RMII reference
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- description: GMAC1 RGMII RX
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- description: External I2S TX bit clock
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- description: External I2S TX left/right channel clock
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- description: External I2S RX bit clock
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- description: External I2S RX left/right channel clock
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- description: External TDM clock
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- description: External audio master clock
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clock-names:
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oneOf:
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- items:
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- const: osc
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- enum:
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- gmac1_rmii_refin
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- gmac1_rgmii_rxin
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- const: i2stx_bclk_ext
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- const: i2stx_lrck_ext
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- const: i2srx_bclk_ext
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- const: i2srx_lrck_ext
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- const: tdm_ext
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- const: mclk_ext
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- items:
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- const: osc
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- const: gmac1_rmii_refin
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- const: gmac1_rgmii_rxin
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- const: i2stx_bclk_ext
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- const: i2stx_lrck_ext
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- const: i2srx_bclk_ext
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- const: i2srx_lrck_ext
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- const: tdm_ext
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- const: mclk_ext
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'#clock-cells':
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const: 1
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description:
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See <dt-bindings/clock/starfive,jh7110-crg.h> for valid indices.
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'#reset-cells':
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const: 1
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description:
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See <dt-bindings/reset/starfive,jh7110-crg.h> for valid indices.
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- '#clock-cells'
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- '#reset-cells'
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additionalProperties: false
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examples:
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- |
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clock-controller@13020000 {
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compatible = "starfive,jh7110-syscrg";
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reg = <0x13020000 0x10000>;
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clocks = <&osc>, <&gmac1_rmii_refin>,
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<&gmac1_rgmii_rxin>,
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<&i2stx_bclk_ext>, <&i2stx_lrck_ext>,
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<&i2srx_bclk_ext>, <&i2srx_lrck_ext>,
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<&tdm_ext>, <&mclk_ext>;
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clock-names = "osc", "gmac1_rmii_refin",
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"gmac1_rgmii_rxin",
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"i2stx_bclk_ext", "i2stx_lrck_ext",
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"i2srx_bclk_ext", "i2srx_lrck_ext",
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"tdm_ext", "mclk_ext";
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#clock-cells = <1>;
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#reset-cells = <1>;
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};

‎Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml‎

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- enum:
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- sifive,fu540-c000-plic
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- starfive,jh7100-plic
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- starfive,jh7110-plic
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- canaan,k210-plic
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- const: sifive,plic-1.0.0
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- items:

‎Documentation/devicetree/bindings/riscv/cpus.yaml‎

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- sifive,e7
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- sifive,e71
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- sifive,rocket0
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- sifive,s7
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- sifive,u5
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- sifive,u54
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- sifive,u7

‎Documentation/devicetree/bindings/timer/sifive,clint.yaml‎

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- enum:
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- sifive,fu540-c000-clint
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- starfive,jh7100-clint
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- starfive,jh7110-clint
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- canaan,k210-clint
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- const: sifive,clint0
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- items:

‎arch/riscv/boot/dts/microchip/mpfs.dtsi‎

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reg = <0x0 0x20002000 0x0 0x1000>, <0x0 0x3E001000 0x0 0x1000>;
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clocks = <&refclk>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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ccc_se: clock-controller@38010000 {
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};
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mac0: ethernet@20110000 {
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compatible = "cdns,macb";
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compatible = "microchip,mpfs-macb", "cdns,macb";
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reg = <0x0 0x20110000 0x0 0x2000>;
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#address-cells = <1>;
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#size-cells = <0>;
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local-mac-address = [00 00 00 00 00 00];
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clocks = <&clkcfg CLK_MAC0>, <&clkcfg CLK_AHB>;
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clock-names = "pclk", "hclk";
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resets = <&clkcfg CLK_MAC0>;
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status = "disabled";
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};
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mac1: ethernet@20112000 {
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compatible = "cdns,macb";
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compatible = "microchip,mpfs-macb", "cdns,macb";
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reg = <0x0 0x20112000 0x0 0x2000>;
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#address-cells = <1>;
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#size-cells = <0>;
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local-mac-address = [00 00 00 00 00 00];
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clocks = <&clkcfg CLK_MAC1>, <&clkcfg CLK_AHB>;
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clock-names = "pclk", "hclk";
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resets = <&clkcfg CLK_MAC1>;
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status = "disabled";
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};
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mbox: mailbox@37020000 {
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compatible = "microchip,mpfs-mailbox";
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reg = <0x0 0x37020000 0x0 0x1000>, <0x0 0x2000318C 0x0 0x40>;
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reg = <0x0 0x37020000 0x0 0x58>, <0x0 0x2000318C 0x0 0x40>,
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<0x0 0x37020800 0x0 0x100>;
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interrupt-parent = <&plic>;
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interrupts = <96>;
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#mbox-cells = <1>;

‎arch/riscv/boot/dts/starfive/Makefile‎

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# SPDX-License-Identifier: GPL-2.0
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dtb-$(CONFIG_ARCH_STARFIVE) += jh7100-beaglev-starlight.dtb jh7100-starfive-visionfive-v1.dtb
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dtb-$(CONFIG_ARCH_STARFIVE) += jh7100-beaglev-starlight.dtb
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dtb-$(CONFIG_ARCH_STARFIVE) += jh7100-starfive-visionfive-v1.dtb
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dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-starfive-visionfive-2-v1.2a.dtb
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dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-starfive-visionfive-2-v1.3b.dtb

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