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Kwiboommind
Kwiboo
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drm/rockchip: vop: Add NV15, NV20 and NV30 support
Add support for displaying 10-bit 4:2:0 and 4:2:2 formats produced by the Rockchip Video Decoder on RK322X, RK3288, RK3328 and RK3399. Also add support for 10-bit 4:4:4 format while at it. V5: Use drm_format_info_min_pitch() for correct bpp Add missing NV21, NV61 and NV42 formats V4: Rework RK3328/RK3399 win0/1 data to not affect RK3368 V2: Added NV30 support Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Sandy Huang <hjc@rock-chips.com> Reviewed-by: Christopher Obbard <chris.obbard@collabora.com> Tested-by: Christopher Obbard <chris.obbard@collabora.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://patchwork.freedesktop.org/patch/msgid/20231023173718.188102-3-jonas@kwiboo.se
1 parent 728c15b commit d4b3842

3 files changed

Lines changed: 86 additions & 17 deletions

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‎drivers/gpu/drm/rockchip/rockchip_drm_vop.c‎

Lines changed: 29 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -272,6 +272,18 @@ static bool has_uv_swapped(uint32_t format)
272272
}
273273
}
274274

275+
static bool is_fmt_10(uint32_t format)
276+
{
277+
switch (format) {
278+
case DRM_FORMAT_NV15:
279+
case DRM_FORMAT_NV20:
280+
case DRM_FORMAT_NV30:
281+
return true;
282+
default:
283+
return false;
284+
}
285+
}
286+
275287
static enum vop_data_format vop_convert_format(uint32_t format)
276288
{
277289
switch (format) {
@@ -287,12 +299,15 @@ static enum vop_data_format vop_convert_format(uint32_t format)
287299
case DRM_FORMAT_BGR565:
288300
return VOP_FMT_RGB565;
289301
case DRM_FORMAT_NV12:
302+
case DRM_FORMAT_NV15:
290303
case DRM_FORMAT_NV21:
291304
return VOP_FMT_YUV420SP;
292305
case DRM_FORMAT_NV16:
306+
case DRM_FORMAT_NV20:
293307
case DRM_FORMAT_NV61:
294308
return VOP_FMT_YUV422SP;
295309
case DRM_FORMAT_NV24:
310+
case DRM_FORMAT_NV30:
296311
case DRM_FORMAT_NV42:
297312
return VOP_FMT_YUV444SP;
298313
default:
@@ -939,7 +954,12 @@ static void vop_plane_atomic_update(struct drm_plane *plane,
939954
dsp_sty = dest->y1 + crtc->mode.vtotal - crtc->mode.vsync_start;
940955
dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff);
941956

942-
offset = (src->x1 >> 16) * fb->format->cpp[0];
957+
if (fb->format->char_per_block[0])
958+
offset = drm_format_info_min_pitch(fb->format, 0,
959+
src->x1 >> 16);
960+
else
961+
offset = (src->x1 >> 16) * fb->format->cpp[0];
962+
943963
offset += (src->y1 >> 16) * fb->pitches[0];
944964
dma_addr = rk_obj->dma_addr + offset + fb->offsets[0];
945965

@@ -965,6 +985,7 @@ static void vop_plane_atomic_update(struct drm_plane *plane,
965985
}
966986

967987
VOP_WIN_SET(vop, win, format, format);
988+
VOP_WIN_SET(vop, win, fmt_10, is_fmt_10(fb->format->format));
968989
VOP_WIN_SET(vop, win, yrgb_vir, DIV_ROUND_UP(fb->pitches[0], 4));
969990
VOP_WIN_SET(vop, win, yrgb_mst, dma_addr);
970991
VOP_WIN_YUV2YUV_SET(vop, win_yuv2yuv, y2r_en, is_yuv);
@@ -974,15 +995,16 @@ static void vop_plane_atomic_update(struct drm_plane *plane,
974995
(new_state->rotation & DRM_MODE_REFLECT_X) ? 1 : 0);
975996

976997
if (is_yuv) {
977-
int hsub = fb->format->hsub;
978-
int vsub = fb->format->vsub;
979-
int bpp = fb->format->cpp[1];
980-
981998
uv_obj = fb->obj[1];
982999
rk_uv_obj = to_rockchip_obj(uv_obj);
9831000

984-
offset = (src->x1 >> 16) * bpp / hsub;
985-
offset += (src->y1 >> 16) * fb->pitches[1] / vsub;
1001+
if (fb->format->char_per_block[1])
1002+
offset = drm_format_info_min_pitch(fb->format, 1,
1003+
src->x1 >> 16);
1004+
else
1005+
offset = (src->x1 >> 16) * fb->format->cpp[1];
1006+
offset /= fb->format->hsub;
1007+
offset += (src->y1 >> 16) * fb->pitches[1] / fb->format->vsub;
9861008

9871009
dma_addr = rk_uv_obj->dma_addr + offset + fb->offsets[1];
9881010
VOP_WIN_SET(vop, win, uv_vir, DIV_ROUND_UP(fb->pitches[1], 4));

‎drivers/gpu/drm/rockchip/rockchip_drm_vop.h‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -186,6 +186,7 @@ struct vop_win_phy {
186186
struct vop_reg enable;
187187
struct vop_reg gate;
188188
struct vop_reg format;
189+
struct vop_reg fmt_10;
189190
struct vop_reg rb_swap;
190191
struct vop_reg uv_swap;
191192
struct vop_reg act_info;

‎drivers/gpu/drm/rockchip/rockchip_vop_reg.c‎

Lines changed: 56 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -53,6 +53,26 @@ static const uint32_t formats_win_full[] = {
5353
DRM_FORMAT_NV42,
5454
};
5555

56+
static const uint32_t formats_win_full_10[] = {
57+
DRM_FORMAT_XRGB8888,
58+
DRM_FORMAT_ARGB8888,
59+
DRM_FORMAT_XBGR8888,
60+
DRM_FORMAT_ABGR8888,
61+
DRM_FORMAT_RGB888,
62+
DRM_FORMAT_BGR888,
63+
DRM_FORMAT_RGB565,
64+
DRM_FORMAT_BGR565,
65+
DRM_FORMAT_NV12,
66+
DRM_FORMAT_NV21,
67+
DRM_FORMAT_NV16,
68+
DRM_FORMAT_NV61,
69+
DRM_FORMAT_NV24,
70+
DRM_FORMAT_NV42,
71+
DRM_FORMAT_NV15,
72+
DRM_FORMAT_NV20,
73+
DRM_FORMAT_NV30,
74+
};
75+
5676
static const uint64_t format_modifiers_win_full[] = {
5777
DRM_FORMAT_MOD_LINEAR,
5878
DRM_FORMAT_MOD_INVALID,
@@ -627,11 +647,12 @@ static const struct vop_scl_regs rk3288_win_full_scl = {
627647

628648
static const struct vop_win_phy rk3288_win01_data = {
629649
.scl = &rk3288_win_full_scl,
630-
.data_formats = formats_win_full,
631-
.nformats = ARRAY_SIZE(formats_win_full),
650+
.data_formats = formats_win_full_10,
651+
.nformats = ARRAY_SIZE(formats_win_full_10),
632652
.format_modifiers = format_modifiers_win_full,
633653
.enable = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 0),
634654
.format = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 1),
655+
.fmt_10 = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 4),
635656
.rb_swap = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 12),
636657
.uv_swap = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 15),
637658
.act_info = VOP_REG(RK3288_WIN0_ACT_INFO, 0x1fff1fff, 0),
@@ -936,13 +957,38 @@ static const struct vop_win_yuv2yuv_data rk3399_vop_big_win_yuv2yuv_data[] = {
936957

937958
};
938959

939-
static const struct vop_win_phy rk3399_win01_data = {
960+
static const struct vop_win_phy rk3399_win0_data = {
940961
.scl = &rk3288_win_full_scl,
941-
.data_formats = formats_win_full,
942-
.nformats = ARRAY_SIZE(formats_win_full),
962+
.data_formats = formats_win_full_10,
963+
.nformats = ARRAY_SIZE(formats_win_full_10),
943964
.format_modifiers = format_modifiers_win_full_afbc,
944965
.enable = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 0),
945966
.format = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 1),
967+
.fmt_10 = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 4),
968+
.rb_swap = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 12),
969+
.uv_swap = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 15),
970+
.x_mir_en = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 21),
971+
.y_mir_en = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 22),
972+
.act_info = VOP_REG(RK3288_WIN0_ACT_INFO, 0x1fff1fff, 0),
973+
.dsp_info = VOP_REG(RK3288_WIN0_DSP_INFO, 0x0fff0fff, 0),
974+
.dsp_st = VOP_REG(RK3288_WIN0_DSP_ST, 0x1fff1fff, 0),
975+
.yrgb_mst = VOP_REG(RK3288_WIN0_YRGB_MST, 0xffffffff, 0),
976+
.uv_mst = VOP_REG(RK3288_WIN0_CBR_MST, 0xffffffff, 0),
977+
.yrgb_vir = VOP_REG(RK3288_WIN0_VIR, 0x3fff, 0),
978+
.uv_vir = VOP_REG(RK3288_WIN0_VIR, 0x3fff, 16),
979+
.src_alpha_ctl = VOP_REG(RK3288_WIN0_SRC_ALPHA_CTRL, 0xff, 0),
980+
.dst_alpha_ctl = VOP_REG(RK3288_WIN0_DST_ALPHA_CTRL, 0xff, 0),
981+
.channel = VOP_REG(RK3288_WIN0_CTRL2, 0xff, 0),
982+
};
983+
984+
static const struct vop_win_phy rk3399_win1_data = {
985+
.scl = &rk3288_win_full_scl,
986+
.data_formats = formats_win_full_10,
987+
.nformats = ARRAY_SIZE(formats_win_full_10),
988+
.format_modifiers = format_modifiers_win_full,
989+
.enable = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 0),
990+
.format = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 1),
991+
.fmt_10 = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 4),
946992
.rb_swap = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 12),
947993
.uv_swap = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 15),
948994
.x_mir_en = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 21),
@@ -965,9 +1011,9 @@ static const struct vop_win_phy rk3399_win01_data = {
9651011
* AFBC on the primary plane.
9661012
*/
9671013
static const struct vop_win_data rk3399_vop_win_data[] = {
968-
{ .base = 0x00, .phy = &rk3399_win01_data,
1014+
{ .base = 0x00, .phy = &rk3399_win0_data,
9691015
.type = DRM_PLANE_TYPE_PRIMARY },
970-
{ .base = 0x40, .phy = &rk3368_win01_data,
1016+
{ .base = 0x40, .phy = &rk3399_win1_data,
9711017
.type = DRM_PLANE_TYPE_OVERLAY },
9721018
{ .base = 0x00, .phy = &rk3368_win23_data,
9731019
.type = DRM_PLANE_TYPE_OVERLAY },
@@ -1099,11 +1145,11 @@ static const struct vop_intr rk3328_vop_intr = {
10991145
};
11001146

11011147
static const struct vop_win_data rk3328_vop_win_data[] = {
1102-
{ .base = 0xd0, .phy = &rk3368_win01_data,
1148+
{ .base = 0xd0, .phy = &rk3399_win1_data,
11031149
.type = DRM_PLANE_TYPE_PRIMARY },
1104-
{ .base = 0x1d0, .phy = &rk3368_win01_data,
1150+
{ .base = 0x1d0, .phy = &rk3399_win1_data,
11051151
.type = DRM_PLANE_TYPE_OVERLAY },
1106-
{ .base = 0x2d0, .phy = &rk3368_win01_data,
1152+
{ .base = 0x2d0, .phy = &rk3399_win1_data,
11071153
.type = DRM_PLANE_TYPE_CURSOR },
11081154
};
11091155

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