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Shenghao-Dingbroonie
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ASoc: PCM6240: Create header file for PCM6240 Family driver code
PCM6240 driver implements a flexible and configurable setting for register and filter coefficients, to one, two or even multiple PCM6240 Family Audio chips. Signed-off-by: Shenghao Ding <shenghao-ding@ti.com> Link: https://lore.kernel.org/r/20240407091846.1299-3-shenghao-ding@ti.com Signed-off-by: Mark Brown <broonie@kernel.org>
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‎sound/soc/codecs/pcm6240.h‎

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/* SPDX-License-Identifier: GPL-2.0 */
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//
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// ALSA SoC Texas Instruments PCM6240 Family Audio ADC/DAC/Router
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//
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// Copyright (C) 2022 - 2024 Texas Instruments Incorporated
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// https://www.ti.com
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//
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// The PCM6240 driver implements a flexible and configurable
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// algo coefficient setting for one, two, or even multiple
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// PCM6240 Family Audio chips.
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//
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// Author: Shenghao Ding <shenghao-ding@ti.com>
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//
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#ifndef __PCM6240_H__
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#define __PCM6240_H__
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enum pcm_device {
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ADC3120,
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ADC5120,
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ADC6120,
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DIX4192,
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PCM1690,
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PCM3120,
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PCM3140,
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PCM5120,
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PCM5140,
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PCM6120,
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PCM6140,
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PCM6240,
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PCM6260,
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PCM9211,
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PCMD3140,
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PCMD3180,
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PCMD512X,
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TAA5212,
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TAA5412,
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TAD5212,
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TAD5412,
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MAX_DEVICE,
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};
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#define PCMDEV_GENERIC_VOL_CTRL 0x0
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#define PCMDEV_PCM1690_VOL_CTRL 0x1
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#define PCMDEV_PCM1690_FINE_VOL_CTRL 0x2
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/* Maximum number of I2C addresses */
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#define PCMDEVICE_MAX_I2C_DEVICES 4
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/* Maximum number defined in REGBIN protocol */
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#define PCMDEVICE_MAX_REGBIN_DEVICES 8
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#define PCMDEVICE_CONFIG_SUM 64
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#define PCMDEVICE_BIN_FILENAME_LEN 64
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#define PCMDEVICE_RATES (SNDRV_PCM_RATE_44100 | \
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SNDRV_PCM_RATE_48000)
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#define PCMDEVICE_MAX_CHANNELS 8
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#define PCMDEVICE_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
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SNDRV_PCM_FMTBIT_S20_3LE | \
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SNDRV_PCM_FMTBIT_S24_3LE | \
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SNDRV_PCM_FMTBIT_S24_LE | \
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SNDRV_PCM_FMTBIT_S32_LE)
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/* PAGE Control Register (available in page0 of each book) */
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#define PCMDEVICE_PAGE_SELECT 0x00
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#define PCMDEVICE_REG(page, reg) ((page * 128) + reg)
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#define PCMDEVICE_REG_SWRESET PCMDEVICE_REG(0X0, 0x01)
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#define PCMDEVICE_REG_SWRESET_RESET BIT(0)
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#define ADC5120_REG_CH1_ANALOG_GAIN PCMDEVICE_REG(0X0, 0x3d)
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#define ADC5120_REG_CH1_DIGITAL_GAIN PCMDEVICE_REG(0X0, 0x3e)
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#define ADC5120_REG_CH2_ANALOG_GAIN PCMDEVICE_REG(0X0, 0x42)
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#define ADC5120_REG_CH2_DIGITAL_GAIN PCMDEVICE_REG(0X0, 0x43)
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#define PCM1690_REG_MODE_CTRL PCMDEVICE_REG(0X0, 0x46)
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#define PCM1690_REG_MODE_CTRL_DAMS_MSK BIT(7)
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#define PCM1690_REG_MODE_CTRL_DAMS_FINE_STEP 0x0
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#define PCM1690_REG_MODE_CTRL_DAMS_WIDE_RANGE 0x80
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#define PCM1690_REG_CH1_DIGITAL_GAIN PCMDEVICE_REG(0X0, 0x48)
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#define PCM1690_REG_CH2_DIGITAL_GAIN PCMDEVICE_REG(0X0, 0x49)
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#define PCM1690_REG_CH3_DIGITAL_GAIN PCMDEVICE_REG(0X0, 0x4a)
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#define PCM1690_REG_CH4_DIGITAL_GAIN PCMDEVICE_REG(0X0, 0x4b)
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#define PCM1690_REG_CH5_DIGITAL_GAIN PCMDEVICE_REG(0X0, 0x4c)
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#define PCM1690_REG_CH6_DIGITAL_GAIN PCMDEVICE_REG(0X0, 0x4d)
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#define PCM1690_REG_CH7_DIGITAL_GAIN PCMDEVICE_REG(0X0, 0x4e)
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#define PCM1690_REG_CH8_DIGITAL_GAIN PCMDEVICE_REG(0X0, 0x4f)
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#define PCM6240_REG_CH1_ANALOG_GAIN PCMDEVICE_REG(0X0, 0x3d)
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#define PCM6240_REG_CH1_DIGITAL_GAIN PCMDEVICE_REG(0X0, 0x3e)
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#define PCM6240_REG_CH2_ANALOG_GAIN PCMDEVICE_REG(0X0, 0x42)
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#define PCM6240_REG_CH2_DIGITAL_GAIN PCMDEVICE_REG(0X0, 0x43)
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#define PCM6240_REG_CH3_ANALOG_GAIN PCMDEVICE_REG(0X0, 0x47)
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#define PCM6240_REG_CH3_DIGITAL_GAIN PCMDEVICE_REG(0X0, 0x48)
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#define PCM6240_REG_CH4_ANALOG_GAIN PCMDEVICE_REG(0X0, 0x4c)
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#define PCM6240_REG_CH4_DIGITAL_GAIN PCMDEVICE_REG(0X0, 0x4d)
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#define PCM6260_REG_CH1_ANALOG_GAIN PCMDEVICE_REG(0X0, 0x3d)
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#define PCM6260_REG_CH1_DIGITAL_GAIN PCMDEVICE_REG(0X0, 0x3e)
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#define PCM6260_REG_CH2_ANALOG_GAIN PCMDEVICE_REG(0X0, 0x42)
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#define PCM6260_REG_CH2_DIGITAL_GAIN PCMDEVICE_REG(0X0, 0x43)
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#define PCM6260_REG_CH3_ANALOG_GAIN PCMDEVICE_REG(0X0, 0x47)
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#define PCM6260_REG_CH3_DIGITAL_GAIN PCMDEVICE_REG(0X0, 0x48)
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#define PCM6260_REG_CH4_ANALOG_GAIN PCMDEVICE_REG(0X0, 0x4c)
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#define PCM6260_REG_CH4_DIGITAL_GAIN PCMDEVICE_REG(0X0, 0x4d)
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#define PCM6260_REG_CH5_ANALOG_GAIN PCMDEVICE_REG(0X0, 0x51)
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#define PCM6260_REG_CH5_DIGITAL_GAIN PCMDEVICE_REG(0X0, 0x52)
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#define PCM6260_REG_CH6_ANALOG_GAIN PCMDEVICE_REG(0X0, 0x56)
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#define PCM6260_REG_CH6_DIGITAL_GAIN PCMDEVICE_REG(0X0, 0x57)
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#define PCM9211_REG_SW_CTRL PCMDEVICE_REG(0X0, 0x40)
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#define PCM9211_REG_SW_CTRL_MRST_MSK BIT(7)
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#define PCM9211_REG_SW_CTRL_MRST 0x0
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#define PCM9211_REG_CH1_DIGITAL_GAIN PCMDEVICE_REG(0X0, 0x46)
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#define PCM9211_REG_CH2_DIGITAL_GAIN PCMDEVICE_REG(0X0, 0x47)
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#define PCMD3140_REG_CH1_DIGITAL_GAIN PCMDEVICE_REG(0X0, 0x3E)
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#define PCMD3140_REG_CH2_DIGITAL_GAIN PCMDEVICE_REG(0X0, 0x43)
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#define PCMD3140_REG_CH3_DIGITAL_GAIN PCMDEVICE_REG(0X0, 0x48)
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#define PCMD3140_REG_CH4_DIGITAL_GAIN PCMDEVICE_REG(0X0, 0x4D)
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#define PCMD3140_REG_CH1_FINE_GAIN PCMDEVICE_REG(0X0, 0x3F)
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#define PCMD3140_REG_CH2_FINE_GAIN PCMDEVICE_REG(0X0, 0x44)
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#define PCMD3140_REG_CH3_FINE_GAIN PCMDEVICE_REG(0X0, 0x49)
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#define PCMD3140_REG_CH4_FINE_GAIN PCMDEVICE_REG(0X0, 0x4E)
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#define PCMD3180_REG_CH1_DIGITAL_GAIN PCMDEVICE_REG(0X0, 0x3E)
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#define PCMD3180_REG_CH2_DIGITAL_GAIN PCMDEVICE_REG(0X0, 0x43)
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#define PCMD3180_REG_CH3_DIGITAL_GAIN PCMDEVICE_REG(0X0, 0x48)
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#define PCMD3180_REG_CH4_DIGITAL_GAIN PCMDEVICE_REG(0X0, 0x4D)
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#define PCMD3180_REG_CH5_DIGITAL_GAIN PCMDEVICE_REG(0X0, 0x52)
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#define PCMD3180_REG_CH6_DIGITAL_GAIN PCMDEVICE_REG(0X0, 0x57)
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#define PCMD3180_REG_CH7_DIGITAL_GAIN PCMDEVICE_REG(0X0, 0x5C)
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#define PCMD3180_REG_CH8_DIGITAL_GAIN PCMDEVICE_REG(0X0, 0x61)
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#define PCMD3180_REG_CH1_FINE_GAIN PCMDEVICE_REG(0X0, 0x3F)
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#define PCMD3180_REG_CH2_FINE_GAIN PCMDEVICE_REG(0X0, 0x44)
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#define PCMD3180_REG_CH3_FINE_GAIN PCMDEVICE_REG(0X0, 0x49)
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#define PCMD3180_REG_CH4_FINE_GAIN PCMDEVICE_REG(0X0, 0x4E)
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#define PCMD3180_REG_CH5_FINE_GAIN PCMDEVICE_REG(0X0, 0x53)
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#define PCMD3180_REG_CH6_FINE_GAIN PCMDEVICE_REG(0X0, 0x58)
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#define PCMD3180_REG_CH7_FINE_GAIN PCMDEVICE_REG(0X0, 0x5D)
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#define PCMD3180_REG_CH8_FINE_GAIN PCMDEVICE_REG(0X0, 0x62)
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#define TAA5412_REG_CH1_DIGITAL_VOLUME PCMDEVICE_REG(0X0, 0x52)
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#define TAA5412_REG_CH2_DIGITAL_VOLUME PCMDEVICE_REG(0X0, 0x57)
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#define TAA5412_REG_CH3_DIGITAL_VOLUME PCMDEVICE_REG(0X0, 0x5B)
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#define TAA5412_REG_CH4_DIGITAL_VOLUME PCMDEVICE_REG(0X0, 0x5F)
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#define TAA5412_REG_CH1_FINE_GAIN PCMDEVICE_REG(0X0, 0x53)
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#define TAA5412_REG_CH2_FINE_GAIN PCMDEVICE_REG(0X0, 0x58)
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#define TAA5412_REG_CH3_FINE_GAIN PCMDEVICE_REG(0X0, 0x5C)
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#define TAA5412_REG_CH4_FINE_GAIN PCMDEVICE_REG(0X0, 0x60)
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#define PCMDEVICE_CMD_SING_W 0x1
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#define PCMDEVICE_CMD_BURST 0x2
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#define PCMDEVICE_CMD_DELAY 0x3
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#define PCMDEVICE_CMD_FIELD_W 0x4
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enum pcmdevice_bin_blk_type {
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PCMDEVICE_BIN_BLK_COEFF = 1,
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PCMDEVICE_BIN_BLK_POST_POWER_UP,
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PCMDEVICE_BIN_BLK_PRE_SHUTDOWN,
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PCMDEVICE_BIN_BLK_PRE_POWER_UP,
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PCMDEVICE_BIN_BLK_POST_SHUTDOWN
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};
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enum pcmdevice_fw_state {
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PCMDEVICE_FW_LOAD_OK = 0,
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PCMDEVICE_FW_LOAD_FAILED
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};
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struct pcmdevice_regbin_hdr {
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unsigned int img_sz;
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unsigned int checksum;
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unsigned int binary_version_num;
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unsigned int drv_fw_version;
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unsigned int timestamp;
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unsigned char plat_type;
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unsigned char dev_family;
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unsigned char reserve;
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unsigned char ndev;
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unsigned char devs[PCMDEVICE_MAX_REGBIN_DEVICES];
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unsigned int nconfig;
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unsigned int config_size[PCMDEVICE_CONFIG_SUM];
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};
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struct pcmdevice_block_data {
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unsigned char dev_idx;
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unsigned char block_type;
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unsigned short yram_checksum;
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unsigned int block_size;
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unsigned int n_subblks;
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unsigned char *regdata;
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};
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struct pcmdevice_config_info {
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char cfg_name[64];
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unsigned int nblocks;
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unsigned int real_nblocks;
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unsigned char active_dev;
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struct pcmdevice_block_data **blk_data;
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};
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struct pcmdevice_regbin {
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struct pcmdevice_regbin_hdr fw_hdr;
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int ncfgs;
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struct pcmdevice_config_info **cfg_info;
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};
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struct pcmdevice_irqinfo {
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int gpio;
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int nmb;
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};
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struct pcmdevice_priv {
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struct snd_soc_component *component;
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struct i2c_client *client;
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struct device *dev;
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struct mutex codec_lock;
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struct gpio_desc *hw_rst;
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struct regmap *regmap;
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struct pcmdevice_regbin regbin;
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struct pcmdevice_irqinfo irq_info;
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unsigned int addr[PCMDEVICE_MAX_I2C_DEVICES];
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unsigned int chip_id;
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int cur_conf;
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int fw_state;
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int ndev;
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unsigned char bin_name[PCMDEVICE_BIN_FILENAME_LEN];
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/* used for kcontrol name */
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unsigned char upper_dev_name[I2C_NAME_SIZE];
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unsigned char dev_name[I2C_NAME_SIZE];
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};
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/* mixer control */
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struct pcmdevice_mixer_control {
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int max;
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int reg;
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unsigned int dev_no;
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unsigned int shift;
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unsigned int invert;
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};
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struct pcmdev_ctrl_info {
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const unsigned int *gain;
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const struct pcmdevice_mixer_control *pcmdev_ctrl;
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unsigned int ctrl_array_size;
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snd_kcontrol_get_t *get;
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snd_kcontrol_put_t *put;
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int pcmdev_ctrl_name_id;
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};
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#endif /* __PCM6240_H__ */

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