|
1836 | 1836 | <&gcc GPLL0_VOTE>, |
1837 | 1837 | <&gcc GPLL1_VOTE>, |
1838 | 1838 | <&rpmcc RPM_SMD_GFX3D_CLK_SRC>, |
1839 | | - <&dsi0_phy 1>, |
1840 | | - <&dsi0_phy 0>, |
1841 | | - <&dsi1_phy 1>, |
1842 | | - <&dsi1_phy 0>, |
| 1839 | + <&mdss_dsi0_phy 1>, |
| 1840 | + <&mdss_dsi0_phy 0>, |
| 1841 | + <&mdss_dsi1_phy 1>, |
| 1842 | + <&mdss_dsi1_phy 0>, |
1843 | 1843 | <0>, |
1844 | 1844 | <0>, |
1845 | 1845 | <0>; |
|
1904 | 1904 | port@0 { |
1905 | 1905 | reg = <0>; |
1906 | 1906 | mdp5_intf1_out: endpoint { |
1907 | | - remote-endpoint = <&dsi0_in>; |
| 1907 | + remote-endpoint = <&mdss_dsi0_in>; |
1908 | 1908 | }; |
1909 | 1909 | }; |
1910 | 1910 |
|
1911 | 1911 | port@1 { |
1912 | 1912 | reg = <1>; |
1913 | 1913 | mdp5_intf2_out: endpoint { |
1914 | | - remote-endpoint = <&dsi1_in>; |
| 1914 | + remote-endpoint = <&mdss_dsi1_in>; |
1915 | 1915 | }; |
1916 | 1916 | }; |
1917 | 1917 | }; |
1918 | 1918 | }; |
1919 | 1919 |
|
1920 | | - dsi0: dsi@fd922800 { |
| 1920 | + mdss_dsi0: dsi@fd922800 { |
1921 | 1921 | compatible = "qcom,msm8974-dsi-ctrl", |
1922 | 1922 | "qcom,mdss-dsi-ctrl"; |
1923 | 1923 | reg = <0xfd922800 0x1f8>; |
|
1927 | 1927 | interrupts = <4>; |
1928 | 1928 |
|
1929 | 1929 | assigned-clocks = <&mmcc BYTE0_CLK_SRC>, <&mmcc PCLK0_CLK_SRC>; |
1930 | | - assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>; |
| 1930 | + assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>; |
1931 | 1931 |
|
1932 | 1932 | clocks = <&mmcc MDSS_MDP_CLK>, |
1933 | 1933 | <&mmcc MDSS_AHB_CLK>, |
|
1944 | 1944 | "core", |
1945 | 1945 | "core_mmss"; |
1946 | 1946 |
|
1947 | | - phys = <&dsi0_phy>; |
| 1947 | + phys = <&mdss_dsi0_phy>; |
1948 | 1948 |
|
1949 | 1949 | status = "disabled"; |
1950 | 1950 |
|
|
1957 | 1957 |
|
1958 | 1958 | port@0 { |
1959 | 1959 | reg = <0>; |
1960 | | - dsi0_in: endpoint { |
| 1960 | + mdss_dsi0_in: endpoint { |
1961 | 1961 | remote-endpoint = <&mdp5_intf1_out>; |
1962 | 1962 | }; |
1963 | 1963 | }; |
1964 | 1964 |
|
1965 | 1965 | port@1 { |
1966 | 1966 | reg = <1>; |
1967 | | - dsi0_out: endpoint { |
| 1967 | + mdss_dsi0_out: endpoint { |
1968 | 1968 | }; |
1969 | 1969 | }; |
1970 | 1970 | }; |
1971 | 1971 | }; |
1972 | 1972 |
|
1973 | | - dsi0_phy: phy@fd922a00 { |
| 1973 | + mdss_dsi0_phy: phy@fd922a00 { |
1974 | 1974 | compatible = "qcom,dsi-phy-28nm-hpm"; |
1975 | 1975 | reg = <0xfd922a00 0xd4>, |
1976 | 1976 | <0xfd922b00 0x280>, |
|
1988 | 1988 | status = "disabled"; |
1989 | 1989 | }; |
1990 | 1990 |
|
1991 | | - dsi1: dsi@fd922e00 { |
| 1991 | + mdss_dsi1: dsi@fd922e00 { |
1992 | 1992 | compatible = "qcom,msm8974-dsi-ctrl", |
1993 | 1993 | "qcom,mdss-dsi-ctrl"; |
1994 | 1994 | reg = <0xfd922e00 0x1f8>; |
|
1998 | 1998 | interrupts = <4>; |
1999 | 1999 |
|
2000 | 2000 | assigned-clocks = <&mmcc BYTE1_CLK_SRC>, <&mmcc PCLK1_CLK_SRC>; |
2001 | | - assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>; |
| 2001 | + assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>; |
2002 | 2002 |
|
2003 | 2003 | clocks = <&mmcc MDSS_MDP_CLK>, |
2004 | 2004 | <&mmcc MDSS_AHB_CLK>, |
|
2015 | 2015 | "core", |
2016 | 2016 | "core_mmss"; |
2017 | 2017 |
|
2018 | | - phys = <&dsi1_phy>; |
| 2018 | + phys = <&mdss_dsi1_phy>; |
2019 | 2019 |
|
2020 | 2020 | status = "disabled"; |
2021 | 2021 |
|
|
2028 | 2028 |
|
2029 | 2029 | port@0 { |
2030 | 2030 | reg = <0>; |
2031 | | - dsi1_in: endpoint { |
| 2031 | + mdss_dsi1_in: endpoint { |
2032 | 2032 | remote-endpoint = <&mdp5_intf2_out>; |
2033 | 2033 | }; |
2034 | 2034 | }; |
2035 | 2035 |
|
2036 | 2036 | port@1 { |
2037 | 2037 | reg = <1>; |
2038 | | - dsi1_out: endpoint { |
| 2038 | + mdss_dsi1_out: endpoint { |
2039 | 2039 | }; |
2040 | 2040 | }; |
2041 | 2041 | }; |
2042 | 2042 | }; |
2043 | 2043 |
|
2044 | | - dsi1_phy: phy@fd923000 { |
| 2044 | + mdss_dsi1_phy: phy@fd923000 { |
2045 | 2045 | compatible = "qcom,dsi-phy-28nm-hpm"; |
2046 | 2046 | reg = <0xfd923000 0xd4>, |
2047 | 2047 | <0xfd923100 0x280>, |
|
0 commit comments