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Nicholas Kazlauskasalexdeucher
Nicholas Kazlauskas
authored and
alexdeucher
committed
drm/amd/display: Revert "Improve x86 and dmub ips handshake"
This reverts commit 1288d70. Causes intermittent hangs during reboot stress testing. Reviewed-by: Duncan Ma <duncan.ma@amd.com> Acked-by: Roman Li <roman.li@amd.com> Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
1 parent 543068f commit d5f9a92

11 files changed

Lines changed: 27 additions & 129 deletions

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‎drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c‎

Lines changed: 0 additions & 37 deletions
Original file line numberDiff line numberDiff line change
@@ -808,34 +808,6 @@ static void dcn35_set_low_power_state(struct clk_mgr *clk_mgr_base)
808808
}
809809
}
810810

811-
static void dcn35_set_idle_state(struct clk_mgr *clk_mgr_base, bool allow_idle)
812-
{
813-
struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
814-
struct dc *dc = clk_mgr_base->ctx->dc;
815-
uint32_t val = dcn35_smu_read_ips_scratch(clk_mgr);
816-
817-
if (dc->config.disable_ips == 0) {
818-
val |= DMUB_IPS1_ALLOW_MASK;
819-
val |= DMUB_IPS2_ALLOW_MASK;
820-
} else if (dc->config.disable_ips == DMUB_IPS_DISABLE_IPS1) {
821-
val = val & ~DMUB_IPS1_ALLOW_MASK;
822-
val = val & ~DMUB_IPS2_ALLOW_MASK;
823-
} else if (dc->config.disable_ips == DMUB_IPS_DISABLE_IPS2) {
824-
val |= DMUB_IPS1_ALLOW_MASK;
825-
val = val & ~DMUB_IPS2_ALLOW_MASK;
826-
} else if (dc->config.disable_ips == DMUB_IPS_DISABLE_IPS2_Z10) {
827-
val |= DMUB_IPS1_ALLOW_MASK;
828-
val |= DMUB_IPS2_ALLOW_MASK;
829-
}
830-
831-
if (!allow_idle) {
832-
val = val & ~DMUB_IPS1_ALLOW_MASK;
833-
val = val & ~DMUB_IPS2_ALLOW_MASK;
834-
}
835-
836-
dcn35_smu_write_ips_scratch(clk_mgr, val);
837-
}
838-
839811
static void dcn35_exit_low_power_state(struct clk_mgr *clk_mgr_base)
840812
{
841813
struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
@@ -855,13 +827,6 @@ static bool dcn35_is_ips_supported(struct clk_mgr *clk_mgr_base)
855827
return ips_supported;
856828
}
857829

858-
static uint32_t dcn35_get_idle_state(struct clk_mgr *clk_mgr_base)
859-
{
860-
struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
861-
862-
return dcn35_smu_read_ips_scratch(clk_mgr);
863-
}
864-
865830
static void dcn35_init_clocks_fpga(struct clk_mgr *clk_mgr)
866831
{
867832
dcn35_init_clocks(clk_mgr);
@@ -949,8 +914,6 @@ static struct clk_mgr_funcs dcn35_funcs = {
949914
.set_low_power_state = dcn35_set_low_power_state,
950915
.exit_low_power_state = dcn35_exit_low_power_state,
951916
.is_ips_supported = dcn35_is_ips_supported,
952-
.set_idle_state = dcn35_set_idle_state,
953-
.get_idle_state = dcn35_get_idle_state
954917
};
955918

956919
struct clk_mgr_funcs dcn35_fpga_funcs = {

‎drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c‎

Lines changed: 2 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -444,9 +444,9 @@ void dcn35_vbios_smu_enable_48mhz_tmdp_refclk_pwrdwn(struct clk_mgr_internal *cl
444444
enable);
445445
}
446446

447-
int dcn35_smu_exit_low_power_state(struct clk_mgr_internal *clk_mgr)
447+
void dcn35_smu_exit_low_power_state(struct clk_mgr_internal *clk_mgr)
448448
{
449-
return dcn35_smu_send_msg_with_param(
449+
dcn35_smu_send_msg_with_param(
450450
clk_mgr,
451451
VBIOSSMC_MSG_DispPsrExit,
452452
0);
@@ -459,13 +459,3 @@ int dcn35_smu_get_ips_supported(struct clk_mgr_internal *clk_mgr)
459459
VBIOSSMC_MSG_QueryIPS2Support,
460460
0);
461461
}
462-
463-
void dcn35_smu_write_ips_scratch(struct clk_mgr_internal *clk_mgr, uint32_t param)
464-
{
465-
REG_WRITE(MP1_SMN_C2PMSG_71, param);
466-
}
467-
468-
uint32_t dcn35_smu_read_ips_scratch(struct clk_mgr_internal *clk_mgr)
469-
{
470-
return REG_READ(MP1_SMN_C2PMSG_71);
471-
}

‎drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.h‎

Lines changed: 1 addition & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -194,10 +194,8 @@ void dcn35_smu_set_zstate_support(struct clk_mgr_internal *clk_mgr, enum dcn_zst
194194
void dcn35_smu_set_dtbclk(struct clk_mgr_internal *clk_mgr, bool enable);
195195
void dcn35_vbios_smu_enable_48mhz_tmdp_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable);
196196

197-
int dcn35_smu_exit_low_power_state(struct clk_mgr_internal *clk_mgr);
197+
void dcn35_smu_exit_low_power_state(struct clk_mgr_internal *clk_mgr);
198198
int dcn35_smu_get_ips_supported(struct clk_mgr_internal *clk_mgr);
199199
int dcn35_smu_get_dtbclk(struct clk_mgr_internal *clk_mgr);
200200
int dcn35_smu_get_dprefclk(struct clk_mgr_internal *clk_mgr);
201-
void dcn35_smu_write_ips_scratch(struct clk_mgr_internal *clk_mgr, uint32_t param);
202-
uint32_t dcn35_smu_read_ips_scratch(struct clk_mgr_internal *clk_mgr);
203201
#endif /* DAL_DC_35_SMU_H_ */

‎drivers/gpu/drm/amd/display/dc/dc.h‎

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -975,8 +975,6 @@ struct dc_debug_options {
975975
bool replay_skip_crtc_disabled;
976976
bool ignore_pg;/*do nothing, let pmfw control it*/
977977
bool psp_disabled_wa;
978-
unsigned int ips2_eval_delay_us;
979-
unsigned int ips2_entry_delay_us;
980978
};
981979

982980
struct gpu_info_soc_bounding_box_v1_0;

‎drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c‎

Lines changed: 12 additions & 45 deletions
Original file line numberDiff line numberDiff line change
@@ -1100,64 +1100,31 @@ void dc_dmub_srv_notify_idle(const struct dc *dc, bool allow_idle)
11001100

11011101
cmd.idle_opt_notify_idle.cntl_data.driver_idle = allow_idle;
11021102

1103-
if (allow_idle) {
1104-
if (dc->hwss.set_idle_state)
1105-
dc->hwss.set_idle_state(dc, true);
1106-
}
1107-
11081103
dm_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);
1104+
1105+
if (allow_idle)
1106+
udelay(500);
11091107
}
11101108

11111109
void dc_dmub_srv_exit_low_power_state(const struct dc *dc)
11121110
{
1113-
uint32_t allow_state = 0;
1114-
uint32_t commit_state = 0;
1115-
11161111
if (dc->debug.dmcub_emulation)
11171112
return;
11181113

11191114
if (!dc->idle_optimizations_allowed)
11201115
return;
11211116

1122-
if (dc->hwss.get_idle_state &&
1123-
dc->hwss.set_idle_state &&
1124-
dc->clk_mgr->funcs->exit_low_power_state) {
1125-
1126-
allow_state = dc->hwss.get_idle_state(dc);
1127-
dc->hwss.set_idle_state(dc, false);
1128-
1129-
if (allow_state & DMUB_IPS2_ALLOW_MASK) {
1130-
// Wait for evaluation time
1131-
udelay(dc->debug.ips2_eval_delay_us);
1132-
commit_state = dc->hwss.get_idle_state(dc);
1133-
if (commit_state & DMUB_IPS2_COMMIT_MASK) {
1134-
// Tell PMFW to exit low power state
1135-
dc->clk_mgr->funcs->exit_low_power_state(dc->clk_mgr);
1136-
1137-
// Wait for IPS2 entry upper bound
1138-
udelay(dc->debug.ips2_entry_delay_us);
1139-
dc->clk_mgr->funcs->exit_low_power_state(dc->clk_mgr);
1117+
// Tell PMFW to exit low power state
1118+
if (dc->clk_mgr->funcs->exit_low_power_state)
1119+
dc->clk_mgr->funcs->exit_low_power_state(dc->clk_mgr);
11401120

1141-
do {
1142-
commit_state = dc->hwss.get_idle_state(dc);
1143-
} while (commit_state & DMUB_IPS2_COMMIT_MASK);
1121+
// Wait for dmcub to load up
1122+
dc_dmub_srv_is_hw_pwr_up(dc->ctx->dmub_srv, true);
11441123

1145-
if (!dc_dmub_srv_is_hw_pwr_up(dc->ctx->dmub_srv, true))
1146-
ASSERT(0);
1147-
1148-
return;
1149-
}
1150-
}
1151-
1152-
dc_dmub_srv_notify_idle(dc, false);
1153-
if (allow_state & DMUB_IPS1_ALLOW_MASK) {
1154-
do {
1155-
commit_state = dc->hwss.get_idle_state(dc);
1156-
} while (commit_state & DMUB_IPS1_COMMIT_MASK);
1157-
}
1158-
}
1124+
// Notify dmcub disallow idle
1125+
dc_dmub_srv_notify_idle(dc, false);
11591126

1160-
if (!dc_dmub_srv_is_hw_pwr_up(dc->ctx->dmub_srv, true))
1161-
ASSERT(0);
1127+
// Confirm dmu is powered up
1128+
dc_dmub_srv_is_hw_pwr_up(dc->ctx->dmub_srv, true);
11621129
}
11631130

‎drivers/gpu/drm/amd/display/dc/dcn35/dcn35_init.c‎

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -120,8 +120,6 @@ static const struct hw_sequencer_funcs dcn35_funcs = {
120120
.calc_blocks_to_ungate = dcn35_calc_blocks_to_ungate,
121121
.block_power_control = dcn35_block_power_control,
122122
.root_clock_control = dcn35_root_clock_control,
123-
.set_idle_state = dcn35_set_idle_state,
124-
.get_idle_state = dcn35_get_idle_state
125123
};
126124

127125
static const struct hwseq_private_funcs dcn35_private_funcs = {

‎drivers/gpu/drm/amd/display/dc/dcn35/dcn35_resource.c‎

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -748,8 +748,6 @@ static const struct dc_debug_options debug_defaults_drv = {
748748
.disable_z10 = false,
749749
.ignore_pg = true,
750750
.psp_disabled_wa = true,
751-
.ips2_eval_delay_us = 200,
752-
.ips2_entry_delay_us = 400
753751
};
754752

755753
static const struct dc_panel_config panel_config_defaults = {

‎drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c‎

Lines changed: 11 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -652,10 +652,18 @@ bool dcn35_apply_idle_power_optimizations(struct dc *dc, bool enable)
652652

653653
// TODO: review other cases when idle optimization is allowed
654654

655+
if (!enable) {
656+
// Tell PMFW to exit low power state
657+
if (dc->clk_mgr->funcs->exit_low_power_state)
658+
dc->clk_mgr->funcs->exit_low_power_state(dc->clk_mgr);
659+
660+
dc_dmub_srv_is_hw_pwr_up(dc->ctx->dmub_srv, true);
661+
}
662+
663+
dc_dmub_srv_notify_idle(dc, enable);
664+
655665
if (!enable)
656-
dc_dmub_srv_exit_low_power_state(dc);
657-
else
658-
dc_dmub_srv_notify_idle(dc, enable);
666+
dc_dmub_srv_is_hw_pwr_up(dc->ctx->dmub_srv, true);
659667

660668
return true;
661669
}
@@ -1189,19 +1197,3 @@ void dcn35_optimize_bandwidth(
11891197
dc->hwss.root_clock_control(dc, &pg_update_state, false);
11901198
}
11911199
}
1192-
1193-
void dcn35_set_idle_state(const struct dc *dc, bool allow_idle)
1194-
{
1195-
// TODO: Find a more suitable communcation
1196-
if (dc->clk_mgr->funcs->set_idle_state)
1197-
dc->clk_mgr->funcs->set_idle_state(dc->clk_mgr, allow_idle);
1198-
}
1199-
1200-
uint32_t dcn35_get_idle_state(const struct dc *dc)
1201-
{
1202-
// TODO: Find a more suitable communcation
1203-
if (dc->clk_mgr->funcs->get_idle_state)
1204-
return dc->clk_mgr->funcs->get_idle_state(dc->clk_mgr);
1205-
1206-
return 0;
1207-
}

‎drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h‎

Lines changed: 0 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -81,7 +81,4 @@ void dcn35_dsc_pg_control(
8181
struct dce_hwseq *hws,
8282
unsigned int dsc_inst,
8383
bool power_on);
84-
85-
void dcn35_set_idle_state(const struct dc *dc, bool allow_idle);
86-
uint32_t dcn35_get_idle_state(const struct dc *dc);
8784
#endif /* __DC_HWSS_DCN35_H__ */

‎drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h‎

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -418,8 +418,7 @@ struct hw_sequencer_funcs {
418418
struct pg_block_update *update_state, bool power_on);
419419
void (*root_clock_control)(struct dc *dc,
420420
struct pg_block_update *update_state, bool power_on);
421-
void (*set_idle_state)(const struct dc *dc, bool allow_idle);
422-
uint32_t (*get_idle_state)(const struct dc *dc);
421+
423422
bool (*is_pipe_topology_transition_seamless)(struct dc *dc,
424423
const struct dc_state *cur_ctx,
425424
const struct dc_state *new_ctx);

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