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lumagAbhinav Kumar
lumag
authored and
Abhinav Kumar
committed
drm/msm/dpu: don't use DPU_CLK_CTRL_CURSORn for DMA SSPP clocks
DPU driver has been using the DPU_CLK_CTRL_CURSOR prefix for the DMA SSPP blocks used for the cursor planes. This has lead to the confusion at least for the MSM8998 platform. In preparation to supporting the cursor SSPP blocks, use proper enum values to index DMA SSPP clock controls. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550 on top of next-20230116 Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/522228/ Link: https://lore.kernel.org/r/20230211231259.1308718-14-dmitry.baryshkov@linaro.org Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
1 parent 0abb6a2 commit d6181c1

2 files changed

Lines changed: 34 additions & 32 deletions

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‎drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c‎

Lines changed: 32 additions & 32 deletions
Original file line numberDiff line numberDiff line change
@@ -525,9 +525,9 @@ static const struct dpu_mdp_cfg sdm845_mdp[] = {
525525
.reg_off = 0x2AC, .bit_off = 8},
526526
.clk_ctrls[DPU_CLK_CTRL_DMA1] = {
527527
.reg_off = 0x2B4, .bit_off = 8},
528-
.clk_ctrls[DPU_CLK_CTRL_CURSOR0] = {
528+
.clk_ctrls[DPU_CLK_CTRL_DMA2] = {
529529
.reg_off = 0x2BC, .bit_off = 8},
530-
.clk_ctrls[DPU_CLK_CTRL_CURSOR1] = {
530+
.clk_ctrls[DPU_CLK_CTRL_DMA3] = {
531531
.reg_off = 0x2C4, .bit_off = 8},
532532
},
533533
};
@@ -542,9 +542,9 @@ static const struct dpu_mdp_cfg sc7180_mdp[] = {
542542
.reg_off = 0x2AC, .bit_off = 0},
543543
.clk_ctrls[DPU_CLK_CTRL_DMA0] = {
544544
.reg_off = 0x2AC, .bit_off = 8},
545-
.clk_ctrls[DPU_CLK_CTRL_CURSOR0] = {
545+
.clk_ctrls[DPU_CLK_CTRL_DMA1] = {
546546
.reg_off = 0x2B4, .bit_off = 8},
547-
.clk_ctrls[DPU_CLK_CTRL_CURSOR1] = {
547+
.clk_ctrls[DPU_CLK_CTRL_DMA2] = {
548548
.reg_off = 0x2C4, .bit_off = 8},
549549
.clk_ctrls[DPU_CLK_CTRL_WB2] = {
550550
.reg_off = 0x3B8, .bit_off = 24},
@@ -569,9 +569,9 @@ static const struct dpu_mdp_cfg sc8180x_mdp[] = {
569569
.reg_off = 0x2AC, .bit_off = 8},
570570
.clk_ctrls[DPU_CLK_CTRL_DMA1] = {
571571
.reg_off = 0x2B4, .bit_off = 8},
572-
.clk_ctrls[DPU_CLK_CTRL_CURSOR0] = {
572+
.clk_ctrls[DPU_CLK_CTRL_DMA2] = {
573573
.reg_off = 0x2BC, .bit_off = 8},
574-
.clk_ctrls[DPU_CLK_CTRL_CURSOR1] = {
574+
.clk_ctrls[DPU_CLK_CTRL_DMA3] = {
575575
.reg_off = 0x2C4, .bit_off = 8},
576576
},
577577
};
@@ -609,9 +609,9 @@ static const struct dpu_mdp_cfg sm8250_mdp[] = {
609609
.reg_off = 0x2AC, .bit_off = 8},
610610
.clk_ctrls[DPU_CLK_CTRL_DMA1] = {
611611
.reg_off = 0x2B4, .bit_off = 8},
612-
.clk_ctrls[DPU_CLK_CTRL_CURSOR0] = {
612+
.clk_ctrls[DPU_CLK_CTRL_DMA2] = {
613613
.reg_off = 0x2BC, .bit_off = 8},
614-
.clk_ctrls[DPU_CLK_CTRL_CURSOR1] = {
614+
.clk_ctrls[DPU_CLK_CTRL_DMA3] = {
615615
.reg_off = 0x2C4, .bit_off = 8},
616616
.clk_ctrls[DPU_CLK_CTRL_REG_DMA] = {
617617
.reg_off = 0x2BC, .bit_off = 20},
@@ -638,9 +638,9 @@ static const struct dpu_mdp_cfg sm8350_mdp[] = {
638638
.reg_off = 0x2ac, .bit_off = 8},
639639
.clk_ctrls[DPU_CLK_CTRL_DMA1] = {
640640
.reg_off = 0x2b4, .bit_off = 8},
641-
.clk_ctrls[DPU_CLK_CTRL_CURSOR0] = {
641+
.clk_ctrls[DPU_CLK_CTRL_DMA2] = {
642642
.reg_off = 0x2bc, .bit_off = 8},
643-
.clk_ctrls[DPU_CLK_CTRL_CURSOR1] = {
643+
.clk_ctrls[DPU_CLK_CTRL_DMA3] = {
644644
.reg_off = 0x2c4, .bit_off = 8},
645645
.clk_ctrls[DPU_CLK_CTRL_REG_DMA] = {
646646
.reg_off = 0x2bc, .bit_off = 20},
@@ -666,9 +666,9 @@ static const struct dpu_mdp_cfg sm8450_mdp[] = {
666666
.reg_off = 0x2AC, .bit_off = 8},
667667
.clk_ctrls[DPU_CLK_CTRL_DMA1] = {
668668
.reg_off = 0x2B4, .bit_off = 8},
669-
.clk_ctrls[DPU_CLK_CTRL_CURSOR0] = {
669+
.clk_ctrls[DPU_CLK_CTRL_DMA2] = {
670670
.reg_off = 0x2BC, .bit_off = 8},
671-
.clk_ctrls[DPU_CLK_CTRL_CURSOR1] = {
671+
.clk_ctrls[DPU_CLK_CTRL_DMA3] = {
672672
.reg_off = 0x2C4, .bit_off = 8},
673673
.clk_ctrls[DPU_CLK_CTRL_REG_DMA] = {
674674
.reg_off = 0x2BC, .bit_off = 20},
@@ -685,9 +685,9 @@ static const struct dpu_mdp_cfg sc7280_mdp[] = {
685685
.reg_off = 0x2AC, .bit_off = 0},
686686
.clk_ctrls[DPU_CLK_CTRL_DMA0] = {
687687
.reg_off = 0x2AC, .bit_off = 8},
688-
.clk_ctrls[DPU_CLK_CTRL_CURSOR0] = {
688+
.clk_ctrls[DPU_CLK_CTRL_DMA1] = {
689689
.reg_off = 0x2B4, .bit_off = 8},
690-
.clk_ctrls[DPU_CLK_CTRL_CURSOR1] = {
690+
.clk_ctrls[DPU_CLK_CTRL_DMA2] = {
691691
.reg_off = 0x2C4, .bit_off = 8},
692692
},
693693
};
@@ -705,8 +705,8 @@ static const struct dpu_mdp_cfg sc8280xp_mdp[] = {
705705
.clk_ctrls[DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0},
706706
.clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8},
707707
.clk_ctrls[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8},
708-
.clk_ctrls[DPU_CLK_CTRL_CURSOR0] = { .reg_off = 0x2bc, .bit_off = 8},
709-
.clk_ctrls[DPU_CLK_CTRL_CURSOR1] = { .reg_off = 0x2c4, .bit_off = 8},
708+
.clk_ctrls[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8},
709+
.clk_ctrls[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8},
710710
.clk_ctrls[DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20},
711711
},
712712
};
@@ -734,9 +734,9 @@ static const struct dpu_mdp_cfg sm8550_mdp[] = {
734734
.reg_off = 0x28330, .bit_off = 0},
735735
.clk_ctrls[DPU_CLK_CTRL_DMA3] = {
736736
.reg_off = 0x2a330, .bit_off = 0},
737-
.clk_ctrls[DPU_CLK_CTRL_CURSOR0] = {
737+
.clk_ctrls[DPU_CLK_CTRL_DMA4] = {
738738
.reg_off = 0x2c330, .bit_off = 0},
739-
.clk_ctrls[DPU_CLK_CTRL_CURSOR1] = {
739+
.clk_ctrls[DPU_CLK_CTRL_DMA5] = {
740740
.reg_off = 0x2e330, .bit_off = 0},
741741
.clk_ctrls[DPU_CLK_CTRL_REG_DMA] = {
742742
.reg_off = 0x2bc, .bit_off = 20},
@@ -1209,9 +1209,9 @@ static const struct dpu_sspp_cfg sdm845_sspp[] = {
12091209
SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, DMA_SDM845_MASK,
12101210
sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1),
12111211
SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, DMA_CURSOR_SDM845_MASK,
1212-
sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0),
1212+
sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2),
12131213
SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, DMA_CURSOR_SDM845_MASK,
1214-
sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1),
1214+
sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA3),
12151215
};
12161216

12171217
static const struct dpu_sspp_sub_blks sc7180_vig_sblk_0 =
@@ -1226,9 +1226,9 @@ static const struct dpu_sspp_cfg sc7180_sspp[] = {
12261226
SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, DMA_SDM845_MASK,
12271227
sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
12281228
SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, DMA_CURSOR_SDM845_MASK,
1229-
sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0),
1229+
sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1),
12301230
SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, DMA_CURSOR_SDM845_MASK,
1231-
sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1),
1231+
sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2),
12321232
};
12331233

12341234
static const struct dpu_sspp_sub_blks sm6115_vig_sblk_0 =
@@ -1264,9 +1264,9 @@ static const struct dpu_sspp_cfg sm8250_sspp[] = {
12641264
SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, DMA_SDM845_MASK,
12651265
sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1),
12661266
SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, DMA_CURSOR_SDM845_MASK,
1267-
sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0),
1267+
sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2),
12681268
SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, DMA_CURSOR_SDM845_MASK,
1269-
sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1),
1269+
sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA3),
12701270
};
12711271

12721272
static const struct dpu_sspp_sub_blks sm8450_vig_sblk_0 =
@@ -1292,9 +1292,9 @@ static const struct dpu_sspp_cfg sm8450_sspp[] = {
12921292
SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, DMA_SDM845_MASK,
12931293
sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1),
12941294
SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, DMA_CURSOR_SDM845_MASK,
1295-
sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0),
1295+
sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2),
12961296
SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, DMA_CURSOR_SDM845_MASK,
1297-
sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1),
1297+
sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA3),
12981298
};
12991299

13001300
static const struct dpu_sspp_sub_blks sm8550_vig_sblk_0 =
@@ -1326,9 +1326,9 @@ static const struct dpu_sspp_cfg sm8550_sspp[] = {
13261326
SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, DMA_SDM845_MASK,
13271327
sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA3),
13281328
SSPP_BLK("sspp_12", SSPP_DMA4, 0x2c000, DMA_CURSOR_SDM845_MASK,
1329-
sm8550_dma_sblk_4, 14, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0),
1329+
sm8550_dma_sblk_4, 14, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA4),
13301330
SSPP_BLK("sspp_13", SSPP_DMA5, 0x2e000, DMA_CURSOR_SDM845_MASK,
1331-
sm8550_dma_sblk_5, 15, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1),
1331+
sm8550_dma_sblk_5, 15, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA5),
13321332
};
13331333

13341334
static const struct dpu_sspp_cfg sc7280_sspp[] = {
@@ -1337,9 +1337,9 @@ static const struct dpu_sspp_cfg sc7280_sspp[] = {
13371337
SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, DMA_SDM845_MASK,
13381338
sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
13391339
SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, DMA_CURSOR_SDM845_MASK,
1340-
sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0),
1340+
sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1),
13411341
SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, DMA_CURSOR_SDM845_MASK,
1342-
sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1),
1342+
sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2),
13431343
};
13441344

13451345
static const struct dpu_sspp_sub_blks sc8280xp_vig_sblk_0 =
@@ -1365,9 +1365,9 @@ static const struct dpu_sspp_cfg sc8280xp_sspp[] = {
13651365
SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, DMA_SDM845_MASK,
13661366
sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1),
13671367
SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, DMA_CURSOR_SDM845_MASK,
1368-
sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0),
1368+
sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2),
13691369
SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, DMA_CURSOR_SDM845_MASK,
1370-
sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1),
1370+
sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA3),
13711371
};
13721372

13731373
#define _VIG_SBLK_NOSCALE(num, sdma_pri) \

‎drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -515,6 +515,8 @@ enum dpu_clk_ctrl_type {
515515
DPU_CLK_CTRL_DMA1,
516516
DPU_CLK_CTRL_DMA2,
517517
DPU_CLK_CTRL_DMA3,
518+
DPU_CLK_CTRL_DMA4,
519+
DPU_CLK_CTRL_DMA5,
518520
DPU_CLK_CTRL_CURSOR0,
519521
DPU_CLK_CTRL_CURSOR1,
520522
DPU_CLK_CTRL_INLINE_ROT0_SSPP,

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