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6by9mripard
6by9
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drm/vc4: plane: Add support for YUV color encodings and ranges
The BT601/BT709 color encoding and limited vs full range properties were not being exposed, defaulting always to BT601 limited range. Expose the parameters and set the registers appropriately. Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Acked-by: Thomas Zimmermann <tzimmermann@suse.de> Link: https://lore.kernel.org/r/20211215091739.135042-4-maxime@cerno.tech
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2 files changed

Lines changed: 82 additions & 8 deletions

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‎drivers/gpu/drm/vc4/vc4_plane.c‎

Lines changed: 68 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -623,6 +623,51 @@ static int vc4_plane_allocate_lbm(struct drm_plane_state *state)
623623
return 0;
624624
}
625625

626+
/*
627+
* The colorspace conversion matrices are held in 3 entries in the dlist.
628+
* Create an array of them, with entries for each full and limited mode, and
629+
* each supported colorspace.
630+
*/
631+
static const u32 colorspace_coeffs[2][DRM_COLOR_ENCODING_MAX][3] = {
632+
{
633+
/* Limited range */
634+
{
635+
/* BT601 */
636+
SCALER_CSC0_ITR_R_601_5,
637+
SCALER_CSC1_ITR_R_601_5,
638+
SCALER_CSC2_ITR_R_601_5,
639+
}, {
640+
/* BT709 */
641+
SCALER_CSC0_ITR_R_709_3,
642+
SCALER_CSC1_ITR_R_709_3,
643+
SCALER_CSC2_ITR_R_709_3,
644+
}, {
645+
/* BT2020 */
646+
SCALER_CSC0_ITR_R_2020,
647+
SCALER_CSC1_ITR_R_2020,
648+
SCALER_CSC2_ITR_R_2020,
649+
}
650+
}, {
651+
/* Full range */
652+
{
653+
/* JFIF */
654+
SCALER_CSC0_JPEG_JFIF,
655+
SCALER_CSC1_JPEG_JFIF,
656+
SCALER_CSC2_JPEG_JFIF,
657+
}, {
658+
/* BT709 */
659+
SCALER_CSC0_ITR_R_709_3_FR,
660+
SCALER_CSC1_ITR_R_709_3_FR,
661+
SCALER_CSC2_ITR_R_709_3_FR,
662+
}, {
663+
/* BT2020 */
664+
SCALER_CSC0_ITR_R_2020_FR,
665+
SCALER_CSC1_ITR_R_2020_FR,
666+
SCALER_CSC2_ITR_R_2020_FR,
667+
}
668+
}
669+
};
670+
626671
/* Writes out a full display list for an active plane to the plane's
627672
* private dlist state.
628673
*/
@@ -1017,9 +1062,20 @@ static int vc4_plane_mode_set(struct drm_plane *plane,
10171062

10181063
/* Colorspace conversion words */
10191064
if (vc4_state->is_yuv) {
1020-
vc4_dlist_write(vc4_state, SCALER_CSC0_ITR_R_601_5);
1021-
vc4_dlist_write(vc4_state, SCALER_CSC1_ITR_R_601_5);
1022-
vc4_dlist_write(vc4_state, SCALER_CSC2_ITR_R_601_5);
1065+
enum drm_color_encoding color_encoding = state->color_encoding;
1066+
enum drm_color_range color_range = state->color_range;
1067+
const u32 *ccm;
1068+
1069+
if (color_encoding >= DRM_COLOR_ENCODING_MAX)
1070+
color_encoding = DRM_COLOR_YCBCR_BT601;
1071+
if (color_range >= DRM_COLOR_RANGE_MAX)
1072+
color_range = DRM_COLOR_YCBCR_LIMITED_RANGE;
1073+
1074+
ccm = colorspace_coeffs[color_range][color_encoding];
1075+
1076+
vc4_dlist_write(vc4_state, ccm[0]);
1077+
vc4_dlist_write(vc4_state, ccm[1]);
1078+
vc4_dlist_write(vc4_state, ccm[2]);
10231079
}
10241080

10251081
vc4_state->lbm_offset = 0;
@@ -1448,6 +1504,15 @@ struct drm_plane *vc4_plane_init(struct drm_device *dev,
14481504
DRM_MODE_REFLECT_X |
14491505
DRM_MODE_REFLECT_Y);
14501506

1507+
drm_plane_create_color_properties(plane,
1508+
BIT(DRM_COLOR_YCBCR_BT601) |
1509+
BIT(DRM_COLOR_YCBCR_BT709) |
1510+
BIT(DRM_COLOR_YCBCR_BT2020),
1511+
BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) |
1512+
BIT(DRM_COLOR_YCBCR_FULL_RANGE),
1513+
DRM_COLOR_YCBCR_BT709,
1514+
DRM_COLOR_YCBCR_LIMITED_RANGE);
1515+
14511516
return plane;
14521517
}
14531518

‎drivers/gpu/drm/vc4/vc4_regs.h‎

Lines changed: 14 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -975,7 +975,10 @@ enum hvs_pixel_format {
975975
#define SCALER_CSC0_COEF_CR_OFS_SHIFT 0
976976
#define SCALER_CSC0_ITR_R_601_5 0x00f00000
977977
#define SCALER_CSC0_ITR_R_709_3 0x00f00000
978+
#define SCALER_CSC0_ITR_R_2020 0x00f00000
978979
#define SCALER_CSC0_JPEG_JFIF 0x00000000
980+
#define SCALER_CSC0_ITR_R_709_3_FR 0x00000000
981+
#define SCALER_CSC0_ITR_R_2020_FR 0x00000000
979982

980983
/* S2.8 contribution of Cb to Green */
981984
#define SCALER_CSC1_COEF_CB_GRN_MASK VC4_MASK(31, 22)
@@ -990,8 +993,11 @@ enum hvs_pixel_format {
990993
#define SCALER_CSC1_COEF_CR_BLU_MASK VC4_MASK(1, 0)
991994
#define SCALER_CSC1_COEF_CR_BLU_SHIFT 0
992995
#define SCALER_CSC1_ITR_R_601_5 0xe73304a8
993-
#define SCALER_CSC1_ITR_R_709_3 0xf2b784a8
994-
#define SCALER_CSC1_JPEG_JFIF 0xea34a400
996+
#define SCALER_CSC1_ITR_R_709_3 0xf27784a8
997+
#define SCALER_CSC1_ITR_R_2020 0xf43594a8
998+
#define SCALER_CSC1_JPEG_JFIF 0xea349400
999+
#define SCALER_CSC1_ITR_R_709_3_FR 0xf4388400
1000+
#define SCALER_CSC1_ITR_R_2020_FR 0xf5b6d400
9951001

9961002
/* S2.8 contribution of Cb to Red */
9971003
#define SCALER_CSC2_COEF_CB_RED_MASK VC4_MASK(29, 20)
@@ -1002,9 +1008,12 @@ enum hvs_pixel_format {
10021008
/* S2.8 contribution of Cb to Blue */
10031009
#define SCALER_CSC2_COEF_CB_BLU_MASK VC4_MASK(19, 10)
10041010
#define SCALER_CSC2_COEF_CB_BLU_SHIFT 10
1005-
#define SCALER_CSC2_ITR_R_601_5 0x00066204
1006-
#define SCALER_CSC2_ITR_R_709_3 0x00072a1c
1007-
#define SCALER_CSC2_JPEG_JFIF 0x000599c5
1011+
#define SCALER_CSC2_ITR_R_601_5 0x00066604
1012+
#define SCALER_CSC2_ITR_R_709_3 0x00072e1d
1013+
#define SCALER_CSC2_ITR_R_2020 0x0006b624
1014+
#define SCALER_CSC2_JPEG_JFIF 0x00059dc6
1015+
#define SCALER_CSC2_ITR_R_709_3_FR 0x00064ddb
1016+
#define SCALER_CSC2_ITR_R_2020_FR 0x0005e5e2
10081017

10091018
#define SCALER_TPZ0_VERT_RECALC BIT(31)
10101019
#define SCALER_TPZ0_SCALE_MASK VC4_MASK(28, 8)

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